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Message-ID: <nvd4fg4mfd6cdcnqqaqyaqthn5ljuzswplvnslpv2pkuano4mf@yn45t5solwzp>
Date: Mon, 22 Sep 2025 10:54:23 +0100
From: Kiryl Shutsemau <kas@...nel.org>
To: "Upadhyay, Neeraj" <neeraj.upadhyay@....com>
Cc: "Edgecombe, Rick P" <rick.p.edgecombe@...el.com>,
"thomas.lendacky@....com" <thomas.lendacky@....com>, "john.allen@....com" <john.allen@....com>,
"Gao, Chao" <chao.gao@...el.com>, "seanjc@...gle.com" <seanjc@...gle.com>,
"Li, Xiaoyao" <xiaoyao.li@...el.com>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"minipli@...ecurity.net" <minipli@...ecurity.net>, "mlevitsk@...hat.com" <mlevitsk@...hat.com>,
"kvm@...r.kernel.org" <kvm@...r.kernel.org>, "pbonzini@...hat.com" <pbonzini@...hat.com>, naveen.rao@....com
Subject: Re: [PATCH v15 29/41] KVM: SEV: Synchronize MSR_IA32_XSS from the
GHCB when it's valid
On Mon, Sep 22, 2025 at 03:03:59PM +0530, Upadhyay, Neeraj wrote:
>
> >
> > In TDX case, VAPIC state is protected VMM. It covers ISR, so guest can
> > safely check ISR to detect if the exception is external or internal.
> >
> > IIUC, VAPIC state is controlled by VMM in SEV case and ISR is not
> > reliable.
> >
> > I am not sure if Secure AVIC[1] changes the situation for AMD.
> >
> > Neeraj?
> >
>
> For Secure AVIC enabled guests, guest's vAPIC ISR state is not visible to
> (and not controlled by) host or VMM.
In this case, I think you should make ia32_disable() in sme_early_init()
conditional on !Secure AVIC.
--
Kiryl Shutsemau / Kirill A. Shutemov
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