linux-kernel - Re: [PATCH v15 29/41] KVM: SEV: Synchronize MSR_IA32

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Message-ID: <bd8831a3-2a23-43d2-9998-73cd5165716c@amd.com>
Date: Mon, 22 Sep 2025 15:03:59 +0530
From: "Upadhyay, Neeraj" <neeraj.upadhyay@....com>
To: Kiryl Shutsemau <kas@...nel.org>,
 "Edgecombe, Rick P" <rick.p.edgecombe@...el.com>
Cc: "thomas.lendacky@....com" <thomas.lendacky@....com>,
 "john.allen@....com" <john.allen@....com>, "Gao, Chao" <chao.gao@...el.com>,
 "seanjc@...gle.com" <seanjc@...gle.com>, "Li, Xiaoyao"
 <xiaoyao.li@...el.com>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
 "minipli@...ecurity.net" <minipli@...ecurity.net>,
 "mlevitsk@...hat.com" <mlevitsk@...hat.com>,
 "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
 "pbonzini@...hat.com" <pbonzini@...hat.com>, naveen.rao@....com
Subject: Re: [PATCH v15 29/41] KVM: SEV: Synchronize MSR_IA32_XSS from the
 GHCB when it's valid


> 
> In TDX case, VAPIC state is protected VMM. It covers ISR, so guest can
> safely check ISR to detect if the exception is external or internal.
> 
> IIUC, VAPIC state is controlled by VMM in SEV case and ISR is not
> reliable.
> 
> I am not sure if Secure AVIC[1] changes the situation for AMD.
> 
> Neeraj?
> 

For Secure AVIC enabled guests, guest's vAPIC ISR state is not visible 
to (and not controlled by) host or VMM.


- Neeraj