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Message-ID: <2645cv6wayqblq5bi2wablue23kj725rpb5bxnh6fhoydubink@u4cl6bneew5h>
Date: Thu, 25 Sep 2025 23:42:57 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Pankaj Patil <pankaj.patil@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Wesley Cheng <wesley.cheng@....qualcomm.com>
Subject: Re: [PATCH v2 23/24] arm64: dts: qcom: glymur: Add USB support
On Thu, Sep 25, 2025 at 11:58:29AM +0530, Pankaj Patil wrote:
> From: Wesley Cheng <wesley.cheng@....qualcomm.com>
>
> The Glymur USB system contains 3 USB type C ports, and 1 USB multiport
> controller. This encompasses 5 SS USB QMP PHYs (3 combo and 2 uni) and 5
> M31 eUSB2 PHYs. The controllers are SNPS DWC3 based, and will use the
> flattened DWC3 QCOM design.
>
> Signed-off-by: Wesley Cheng <wesley.cheng@....qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 243 ++++++++++++++
> arch/arm64/boot/dts/qcom/glymur.dtsi | 569 ++++++++++++++++++++++++++++++++
> 2 files changed, 812 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> index 03aacdb1dd7e2354fe31e63183519e53fa022829..100519aa5a7cd905285d3aa41ebe5f63ae00aeef 100644
> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> @@ -99,10 +99,74 @@ ports {
>
> port@0 {
> reg = <0>;
> +
> + pmic_glink_hs_in: endpoint {
> + remote-endpoint = <&usb_0_dwc3_hs>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + pmic_glink_ss_in: endpoint {
> + remote-endpoint = <&usb_dp_qmpphy_out>;
> + };
> + };
> + };
> + };
> +
> + connector@1 {
> + compatible = "usb-c-connector";
> + reg = <1>;
> + power-role = "dual";
> + data-role = "dual";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + pmic_glink_hs_in1: endpoint {
> + remote-endpoint = <&usb_1_dwc3_hs>;
> + };
> };
>
> port@1 {
> reg = <1>;
> +
> + pmic_glink_ss_in1: endpoint {
> + remote-endpoint = <&usb_1_ss1_qmpphy_out>;
> + };
> + };
> + };
> + };
> +
> + connector@2 {
> + compatible = "usb-c-connector";
> + reg = <2>;
> + power-role = "dual";
> + data-role = "dual";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + pmic_glink_hs_in2: endpoint {
> + remote-endpoint = <&usb_2_dwc3_hs>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + pmic_glink_ss_in2: endpoint {
> + remote-endpoint = <&usb_1_ss2_qmpphy_out>;
> + };
> };
> };
> };
> @@ -529,3 +593,182 @@ &pcie5port0 {
> perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> };
> +
> +&i2c5 {
> + status = "ok";
> +
> + clock-frequency = <400000>;
> +
> + ptn3222_0: redriver@43 {
> + compatible = "nxp,ptn3222";
> + reg = <0x43>;
> +
> + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
> +
> + vdd3v3-supply = <&vreg_l8b_e0_1p50>;
> + vdd1v8-supply = <&vreg_l15b_e0_1p8>;
> +
> + #phy-cells = <0>;
> + };
> +
> + ptn3222_1: redriver@4f {
> + compatible = "nxp,ptn3222";
> + reg = <0x4f>;
> +
> + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>;
> +
> + vdd3v3-supply = <&vreg_l8b_e0_1p50>;
> + vdd1v8-supply = <&vreg_l15b_e0_1p8>;
> +
> + #phy-cells = <0>;
> + };
> +};
> +
> +&smb2370_j_e2_eusb2_repeater {
> + vdd18-supply = <&vreg_l15b_e0_1p8>;
> + vdd3-supply = <&vreg_l7b_e0_2p79>;
> +};
> +
> +&smb2370_k_e2_eusb2_repeater {
> + vdd18-supply = <&vreg_l15b_e0_1p8>;
> + vdd3-supply = <&vreg_l7b_e0_2p79>;
> +};
> +
> +&smb2370_l_e2_eusb2_repeater {
> + vdd18-supply = <&vreg_l15b_e0_1p8>;
> + vdd3-supply = <&vreg_l7b_e0_2p79>;
> +};
> +
> +&usb_1_ss0_hsphy {
> + vdd-supply = <&vreg_l3f_e0_0p72>;
> + vdda12-supply = <&vreg_l4h_e0_1p2>;
> +
> + phys = <&smb2370_j_e2_eusb2_repeater>;
> +
> + status = "okay";
> +};
> +
> +&usb_1_ss0_qmpphy {
> + vdda-phy-supply = <&vreg_l4h_e0_1p2>;
> + vdda-pll-supply = <&vreg_l3f_e0_0p72>;
> + refgen-supply = <&vreg_l2f_e0_0p82>;
> +
> + status = "okay";
> +};
> +
> +&usb_dp_qmpphy_out {
> + remote-endpoint = <&pmic_glink_ss_in>;
> +};
> +
> +&usb_0_dwc3_hs {
> + remote-endpoint = <&pmic_glink_hs_in>;
> +};
> +
> +&usb_1_ss0 {
> + dr_mode = "otg";
This is a default
> + usb-role-switch;
And this should be a part of the SoC DTSI
> +
> + status = "okay";
> +};
> +
> +&usb_1_ss1_qmpphy_out {
> + remote-endpoint = <&pmic_glink_ss_in1>;
> +};
> +
> +&usb_1_dwc3_hs {
> + remote-endpoint = <&pmic_glink_hs_in1>;
> +};
> +
> +&usb_1_ss1_hsphy {
> + vdd-supply = <&vreg_l3f_e0_0p72>;
> + vdda12-supply = <&vreg_l4h_e0_1p2>;
> +
> + phys = <&smb2370_k_e2_eusb2_repeater>;
> +
> + status = "okay";
> +};
> +
> +&usb_1_ss1_qmpphy {
> + vdda-phy-supply = <&vreg_l4h_e0_1p2>;
> + vdda-pll-supply = <&vreg_l1h_e0_0p89>;
> + refgen-supply = <&vreg_l2f_e0_0p82>;
> +
> + status = "okay";
> +};
> +
> +&usb1_ss1 {
> + dr_mode = "otg";
> + usb-role-switch;
Again, neither of these should be here.
> +
> + status = "okay";
> +};
> +
> +&usb_1_ss2_qmpphy_out {
> + remote-endpoint = <&pmic_glink_ss_in2>;
> +};
> +
> +&usb_2_dwc3_hs {
> + remote-endpoint = <&pmic_glink_hs_in2>;
> +};
> +
> +&usb_1_ss2_hsphy {
> + vdd-supply = <&vreg_l4c_e1_0p72>;
> + vdda12-supply = <&vreg_l4f_e1_1p08>;
> +
> + phys = <&smb2370_l_e2_eusb2_repeater>;
> +
> + status = "okay";
> +};
> +
> +&usb_1_ss2_qmpphy {
> + vdda-phy-supply = <&vreg_l4f_e1_1p08>;
> + vdda-pll-supply = <&vreg_l4c_e1_0p72>;
> + refgen-supply = <&vreg_l1c_e1_0p82>;
> +
> + status = "okay";
> +};
> +
> +&usb1_ss2 {
> + dr_mode = "otg";
> + usb-role-switch;
The same
> +
> + status = "okay";
> +};
> +
> +&usb_mp_hsphy0 {
> + vdd-supply = <&vreg_l2h_e0_0p72>;
> + vdda12-supply = <&vreg_l4h_e0_1p2>;
> +
> + phys = <&ptn3222_0>;
> +
> + status = "okay";
> +};
> +
> +&usb_mp_hsphy1 {
> + vdd-supply = <&vreg_l2h_e0_0p72>;
> + vdda12-supply = <&vreg_l4h_e0_1p2>;
> +
> + phys = <&ptn3222_1>;
> +
> + status = "okay";
> +};
> +
> +&usb_mp_qmpphy0 {
> + vdda-phy-supply = <&vreg_l4h_e0_1p2>;
> + vdda-pll-supply = <&vreg_l2h_e0_0p72>;
> + refgen-supply = <&vreg_l4f_e1_1p08>;
> +
> + status = "okay";
> +};
> +
> +&usb_mp_qmpphy1 {
> + vdda-phy-supply = <&vreg_l4h_e0_1p2>;
> + vdda-pll-supply = <&vreg_l2h_e0_0p72>;
> + refgen-supply = <&vreg_l4f_e1_1p08>;
> +
> + status = "okay";
> +};
> +
> +&usb_mp {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 8a563d55bdd4902222039946dd75eaf4d3a4895b..c48d3a70820e551822c5322761528159da127ca6 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
No update for GCC clock inputs? And that's too easy to miss because of
the patch split.
> @@ -2417,6 +2417,231 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
> };
> };
>
> + usb_mp_hsphy0: phy@...000 {
> + compatible = "qcom,glymur-m31-eusb2-phy",
> + "qcom,sm8750-m31-eusb2-phy";
> +
> + reg = <0 0x00fa1000 0 0x29c>;
> + #phy-cells = <0>;
> +
> + clocks = <&tcsrcc TCSR_USB2_1_CLKREF_EN>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
> +
> + status = "disabled";
> + };
> +
> + usb_mp_hsphy1: phy@...000 {
> + compatible = "qcom,glymur-m31-eusb2-phy",
> + "qcom,sm8750-m31-eusb2-phy";
> +
> + reg = <0 0x00fa2000 0 0x29c>;
> + #phy-cells = <0>;
> +
> + clocks = <&tcsrcc TCSR_USB2_2_CLKREF_EN>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
> +
> + status = "disabled";
> + };
> +
> + usb_mp_qmpphy0: phy@...000 {
> + compatible = "qcom,glymur-qmp-usb3-uni-phy";
> + reg = <0 0x00fa3000 0 0x2000>;
> +
> + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
> + <&tcsrcc TCSR_USB3_0_CLKREF_EN>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
> + clock-names = "aux",
> + "clkref",
> + "ref",
> + "com_aux",
> + "pipe";
> +
> + power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
> +
> + resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>,
> + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
> + reset-names = "phy",
> + "phy_phy";
> +
> + clock-output-names = "usb3_uni_phy_0_pipe_clk_src";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + usb_mp_qmpphy1: phy@...000 {
> + compatible = "qcom,glymur-qmp-usb3-uni-phy";
> + reg = <0 0x00fa5000 0 0x2000>;
> +
> + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
> + <&tcsrcc TCSR_USB3_1_CLKREF_EN>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
> + clock-names = "aux",
> + "clkref",
> + "ref",
> + "com_aux",
> + "pipe";
> +
> + power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
> +
> + resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>,
> + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
> + reset-names = "phy",
> + "phy_phy";
> +
> + clock-output-names = "usb3_uni_phy_1_pipe_clk_src";
> +
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + usb_1_ss0_hsphy: phy@...000 {
> + compatible = "qcom,glymur-m31-eusb2-phy",
> + "qcom,sm8750-m31-eusb2-phy";
> +
> + reg = <0 0x00fd3000 0 0x29c>;
> + #phy-cells = <0>;
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> +
> + status = "disabled";
> + };
> +
> + usb_1_ss0_qmpphy: phy@...000 {
> + compatible = "qcom,glymur-qmp-usb3-dp-phy";
> + reg = <0 0x00fd5000 0 0x8000>;
> +
> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "aux",
> + "ref",
> + "com_aux",
> + "usb3_pipe";
> +
> + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
> +
> + reset-names = "phy",
> + "common";
> +
> + power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <1>;
> +
> + orientation-switch;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + usb_dp_qmpphy_out: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + usb_1_ss0_qmpphy_usb_ss_in: endpoint {
> + remote-endpoint = <&usb_1_ss0>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + usb_dp_qmpphy_dp_in: endpoint {
> + };
> + };
> + };
> + };
> +
> + usb_1_ss1_hsphy: phy@...000 {
> + compatible = "qcom,glymur-m31-eusb2-phy",
> + "qcom,sm8750-m31-eusb2-phy";
> +
> + reg = <0 0x00fdd000 0 0x29c>;
> + #phy-cells = <0>;
> +
> + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
> +
> + status = "disabled";
> + };
> +
> + usb_1_ss1_qmpphy: phy@...000 {
> + compatible = "qcom,glymur-qmp-usb3-dp-phy";
> + reg = <0 0x00fde000 0 0x8000>;
> +
> + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
> + <&tcsrcc TCSR_USB4_1_CLKREF_EN>;
> + clock-names = "aux",
> + "ref",
> + "com_aux",
> + "usb3_pipe",
> + "clkref";
> +
> + power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
> +
> + resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
> + <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
> + reset-names = "phy",
> + "common";
> +
> + #clock-cells = <1>;
> + #phy-cells = <1>;
> + orientation-switch;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + usb_1_ss1_qmpphy_out: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + usb_1_ss1_qmpphy_usb_ss_in: endpoint {
> + remote-endpoint = <&usb1_ss1>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + usb_1_ss1_qmpphy_dp_in: endpoint {
> + };
> + };
> + };
> + };
> +
> cnoc_main: interconnect@...0000 {
> compatible = "qcom,glymur-cnoc-main";
> reg = <0x0 0x01500000 0x0 0x17080>;
> @@ -2777,6 +3002,350 @@ lpass_ag_noc: interconnect@...0000 {
> #interconnect-cells = <2>;
> };
>
> + usb_1_ss2_hsphy: phy@...0000 {
> + compatible = "qcom,glymur-m31-eusb2-phy",
> + "qcom,sm8750-m31-eusb2-phy";
> +
> + reg = <0 0x088e0000 0 0x29c>;
> + #phy-cells = <0>;
> +
> + clocks = <&tcsrcc TCSR_USB2_4_CLKREF_EN>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
> +
> + status = "disabled";
> + };
> +
> + usb_1_ss2_qmpphy: phy@...1000 {
> + compatible = "qcom,glymur-qmp-usb3-dp-phy";
> + reg = <0 0x088e1000 0 0x8000>;
> +
> + clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>,
> + <&tcsrcc TCSR_USB4_2_CLKREF_EN>;
> + clock-names = "aux",
> + "ref",
> + "com_aux",
> + "usb3_pipe",
> + "clkref";
> +
> + power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
> +
> + resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
> + <&gcc GCC_USB3PHY_PHY_TERT_BCR>;
> + reset-names = "phy",
> + "common";
> +
> + #clock-cells = <1>;
> + #phy-cells = <1>;
> + orientation-switch;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + usb_1_ss2_qmpphy_out: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + usb_1_ss2_qmpphy_usb_ss_in: endpoint {
> + remote-endpoint = <&usb1_ss2>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + usb_1_ss2_qmpphy_dp_in: endpoint {
> + };
> + };
> + };
> + };
> +
> + usb_1_ss0: usb@...0000 {
> + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
> + reg = <0 0x0a600000 0 0xfc100>;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
> + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi",
> + "noc_aggr_north",
> + "noc_aggr_south";
> +
> + interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 90 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 60 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
> + interrupt-names = "dwc_usb3",
> + "pwr_event",
> + "dp_hs_phy_irq",
> + "dm_hs_phy_irq",
> + "ss_phy_irq";
> +
> + power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
> + resets = <&gcc GCC_USB30_PRIM_BCR>;
> +
> + iommus = <&apps_smmu 0x1420 0x0>;
> + phys = <&usb_1_ss0_hsphy>,
> + <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
> + phy-names = "usb2-phy",
> + "usb3-phy";
> +
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + snps,dis_u3_susphy_quirk;
> + snps,usb2-lpm-disable;
> +
> + dr_mode = "peripheral";
Why? No.
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + usb_0_dwc3_hs: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + usb_0_dwc3_ss: endpoint {
> + remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
> + };
> + };
> + };
> + };
> +
> + usb1_ss1: usb@...0000 {
> + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
> + reg = <0 0x0a800000 0 0xfc100>;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
> + <&gcc GCC_USB30_SEC_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
> + <&gcc GCC_USB30_SEC_SLEEP_CLK>,
> + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
> + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
> + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi",
> + "noc_aggr_north",
> + "noc_aggr_south";
> +
> + interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 88 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 87 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 76 IRQ_TYPE_EDGE_BOTH>;
> + interrupt-names = "dwc_usb3",
> + "pwr_event",
> + "dp_hs_phy_irq",
> + "dm_hs_phy_irq",
> + "ss_phy_irq";
> +
> + resets = <&gcc GCC_USB30_SEC_BCR>;
> + power-domains = <&gcc GCC_USB30_SEC_GDSC>;
> +
> + iommus = <&apps_smmu 0x1460 0x0>;
> +
> + phys = <&usb_1_ss1_hsphy>,
> + <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
> + phy-names = "usb2-phy",
> + "usb3-phy";
> +
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + snps,dis_u3_susphy_quirk;
> + snps,usb2-lpm-disable;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + usb_1_dwc3_hs: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + usb_1_dwc3_ss: endpoint {
> + remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
> + };
> + };
> + };
> + };
> +
> + usb1_ss2: usb@...0000 {
> + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
> + reg = <0 0x0a000000 0 0xfc100>;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
> + <&gcc GCC_USB30_TERT_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
> + <&gcc GCC_USB30_TERT_SLEEP_CLK>,
> + <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
> + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
> + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi",
> + "noc_aggr_north",
> + "noc_aggr_south";
> +
> + interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 89 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 81 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 75 IRQ_TYPE_EDGE_BOTH>;
> + interrupt-names = "dwc_usb3",
> + "pwr_event",
> + "dp_hs_phy_irq",
> + "dm_hs_phy_irq",
> + "ss_phy_irq";
> +
> + resets = <&gcc GCC_USB30_TERT_BCR>;
> + power-domains = <&gcc GCC_USB30_TERT_GDSC>;
> +
> + iommus = <&apps_smmu 0x420 0x0>;
> +
> + phys = <&usb_1_ss2_hsphy>,
> + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
> + phy-names = "usb2-phy",
> + "usb3-phy";
> +
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + snps,dis_u3_susphy_quirk;
> + snps,usb2-lpm-disable;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + usb_2_dwc3_hs: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + usb_2_dwc3_ss: endpoint {
> + remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
> + };
> + };
> + };
> + };
> +
> + usb_mp: usb@...0000 {
> + compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3";
> + reg = <0 0x0a400000 0 0xfc100>;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
> + <&gcc GCC_USB30_MP_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
> + <&gcc GCC_USB30_MP_SLEEP_CLK>,
> + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
> + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi",
> + "noc_aggr_north",
> + "noc_aggr_south";
> +
> + interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 12 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 11 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 13 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 78 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 77 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "dwc_usb3",
> + "pwr_event_1",
> + "pwr_event_2",
> + "hs_phy_1",
> + "hs_phy_2",
> + "dp_hs_phy_1",
> + "dm_hs_phy_1",
> + "dp_hs_phy_2",
> + "dm_hs_phy_2",
> + "ss_phy_1",
> + "ss_phy_2";
> +
> + resets = <&gcc GCC_USB30_MP_BCR>;
> + power-domains = <&gcc GCC_USB30_MP_GDSC>;
> +
> + iommus = <&apps_smmu 0xda0 0x0>;
> +
> + phys = <&usb_mp_hsphy0>,
> + <&usb_mp_qmpphy0>,
> + <&usb_mp_hsphy1>,
> + <&usb_mp_qmpphy1>;
> + phy-names = "usb2-0",
> + "usb3-0",
> + "usb2-1",
> + "usb3-1";
> +
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + snps,usb3_lpm_capable;
> + snps,dis_u3_susphy_quirk;
> + snps,usb2-lpm-disable;
> +
> + dr_mode = "host";
> +
> + status = "disabled";
> +
> + };
> +
> dispcc: clock-controller@...0000 {
> compatible = "qcom,glymur-dispcc";
> reg = <0 0x0af00000 0 0x20000>;
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
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