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Message-ID: <CAJKOXPc8NYrwSLbaFZ_tRVpgkYPUYhaMde77p1VBhqm9PLsGjA@mail.gmail.com>
Date: Thu, 25 Sep 2025 17:23:07 +0900
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Pankaj Patil <pankaj.patil@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Sibi Sankar <sibi.sankar@....qualcomm.com>
Subject: Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox
On Thu, 25 Sept 2025 at 15:33, Pankaj Patil
<pankaj.patil@....qualcomm.com> wrote:
>
> From: Sibi Sankar <sibi.sankar@....qualcomm.com>
>
> Enable pdp0 mailbox node on Glymur SoCs.
>
> Signed-off-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -4065,6 +4065,14 @@ watchdog@...00000 {
> interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
> };
>
> + pdp0_mbox: mailbox@...10000 {
> + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
> + reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <1>;
> + qcom,rx-chans = <0x7>;
> + };
Again one node per patch. this is really pointless, please read
submitting patches before posting.
New Soc is one logical change. One.
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