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Message-Id: <20250930040348.3702923-3-h.dewangan@samsung.com>
Date: Tue, 30 Sep 2025 09:33:21 +0530
From: Himanshu Dewangan <h.dewangan@...sung.com>
To: mchehab@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, sumit.semwal@...aro.org, christian.koenig@....com,
alim.akhtar@...sung.com, manjun@...sung.com, nagaraju.s@...sung.com,
ih0206.lee@...sung.com, jehyung.lee@...sung.com
Cc: linux-arm-kernel@...ts.infradead.org, linux-media@...r.kernel.org,
devicetree@...r.kernel.org, linux-samsung-soc@...r.kernel.org,
linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linaro-mm-sig@...ts.linaro.org, Himanshu Dewangan <h.dewangan@...sung.com>
Subject: [PATCH 02/29] arm64: dts: mfc: Add MFC device tree for Auto V920
SoC
From: Nagaraju Siddineni <nagaraju.s@...sung.com>
Introduce the device‑tree entries for the Samsung Exynos AUTO V920
multimedia‑function controller (MFC). The patch defines:
- Reserved memory regions for firmware and CMA buffers.
- Core0 and Core1 memory mappings.
- The main MFC node with basic properties (compatible, reg, interrupts,
clocks, DMA window, firmware name, debug mode, etc.).
- Per‑core sub‑nodes (MFC‑0 and MFC‑1) with their own sysmmu,
firmware region, and configuration parameters.
- Resource table listing supported codecs and their capabilities.
Adds full support for the V920 MFC hardware to the mainline kernel
device‑tree, enabling proper memory allocation, interrupt handling and
codec operation on this platform.
Signed-off-by: Nagaraju Siddineni <nagaraju.s@...sung.com>
Signed-off-by: Himanshu Dewangan <h.dewangan@...sung.com>
---
.../dts/exynos/exynosautov920-evt2-mfc.dtsi | 187 ++++++++++++++++++
.../arm64/boot/dts/exynos/exynosautov920.dtsi | 1 +
2 files changed, 188 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi
new file mode 100644
index 000000000000..49c61958467e
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SAMSUNG EXYNOS AUTO V920 SoC MFC device tree source
+ *
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ */
+
+#define MFC_CORE0_MEM_ADDR 0xE9C00000
+#define MFC_CORE1_MEM_ADDR 0xEFB00000
+#define MFC_CMA_MEM_ADDR 0xB0000000
+#define MFC_CMA_MEM_SIZE 0x040000000 /* 64MB */
+#define MFC_FW_MEM_ADDR 0x9F000000
+#define MFC_FW_MEM_SIZE 0x00800000 /* 8MB */
+#define MFC_MEM_SIZE 0x00100000 /* 1MB */
+
+/ {
+reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mfc_fw_rmem: mfc_fw_rmem@...00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 MFC_FW_MEM_ADDR 0x0 MFC_FW_MEM_SIZE>;
+ alignment = <0x0 0x00010000>;
+ reusable;
+ };
+
+ mfc_buf_rmem: mfc_buf_rmem {
+ compatible = "shared-dma-pool";
+ reg = <0x0 MFC_CMA_MEM_ADDR 0x0 MFC_CMA_MEM_SIZE>;
+ alignment = <0x0 0x00010000>;
+ reusable;
+ linux,cma-default;
+ };
+
+ mfc_core0_mem: mfc_core0_mem@...00000 {
+ compatible = "samsung,mfc_core0_mem";
+ reg = <0x0 MFC_CORE0_MEM_ADDR 0x0 MFC_MEM_SIZE>;
+ };
+
+ mfc_core1_mem: mfc_core1_mem@...00000 {
+ compatible = "samsung,mfc_core1_mem";
+ reg = <0x0 MFC_CORE1_MEM_ADDR 0x0 MFC_MEM_SIZE>;
+ };
+};
+
+ mfc: mfc@...d0000 {
+ /* Basic setting */
+ compatible = "samsung,exynos-mfc";
+
+ reg = <0x0 0x19CD0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "aclk_mfc";
+ clocks = <&cmu_top 1900>;
+
+ /* for vb2 device */
+ samsung,tzmp;
+
+ /* for F/W buffer to support 36bit-DMA */
+ memory-region = <&mfc_fw_rmem &mfc_buf_rmem>;
+
+ /* MFC DMA bit (32 or 36) */
+ dma_bit_mask = <32>;
+
+ /* MFC version */
+ ip_ver = <0x1600010C>;
+
+ /* MFC firmware name */
+ fw_name = "mfc_fw_v16.0.bin";
+
+ /* Debug mode */
+ debug_mode = <1>;
+
+ /* Features <on/off version> */
+ mem_clear = <1 0x0>;
+ /* Support from v11.0 (except 11.2) */
+ wait_fw_status = <1 0x190122>;
+
+ /* Scheduler 0: round-robin, 1: PBS */
+ scheduler = <1>;
+ /* The number of priority in PBS */
+ pbs_num_prio = <1>;
+
+ /* MFC IOVA threshold (MB) */
+ iova_threshold = <1700>;
+
+ /* Sub nodes for MFC core */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * Resource of standard
+ * <codec num> MFC_REG_CODEC_XXX
+ * <op core type> 0: MFC only, 1: MFD only, 2: ALL
+ * <max Kbps> 245760: 240Mbps, 122880: 120Mbps, 81920: 80Mbps
+ */
+ mfc_resource {
+ /* codec name { codec mode, op core type, max Kbps } */
+ H264_dec { info = <0 2 245760>; };
+ VP8_dec { info = <14 0 81920>; };
+ HEVC_dec { info = <17 2 245760>; };
+ VP9_dec { info = <18 0 81920>; };
+ AV1_dec { info = <19 1 122880>; };
+ H264_enc { info = <20 0 245760>; };
+ VP8_enc { info = <25 0 81920>; };
+ HEVC_enc { info = <26 0 245760>; };
+ VP9_enc { info = <27 0 81920>; };
+ };
+
+ /* MFC core device */
+ mfc_core0: MFC-0@...d0000 {
+ /* Basic setting */
+ compatible = "samsung,exynos-mfc-core";
+ id = <0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0x0 0x19CD0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "aclk_mfc";
+ clocks = <&cmu_top 1900>;
+ samsung,tzmp;
+
+ /* MFC version */
+ ip_ver = <0x1600010C>;
+
+ /* for F/W buffer */
+ fw-region = <&mfc_core0_mem>;
+
+ /* Sysmmu check */
+ share_sysmmu = <0>;
+ axid_mask = <0xFFFF>;
+ tsmux_axid = <0x1>;
+
+ /* mem-log buffer size */
+ memlog_size = <0x80000>;
+ memlog_sfr_size = <0x1000>;
+
+ /* Device virtual address */
+ #dma-address-cells = <1>;
+ #dma-size-cells = <1>;
+ dma-window = <0x0 0xF0000000>;
+
+ /* Sub nodes for sysmmu, hwfc and mmcache */
+ iommu@...70000 {
+ reg = <0x0 0x19C70000 0x0 0x9000>;
+ };
+ };
+
+ mfc_core1: MFC-1@...d0000 {
+ /* Basic setting */
+ compatible = "samsung,exynos-mfc-core";
+ id = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0x0 0x19ED0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "aclk_mfc";
+ clocks = <&cmu_top 2000>;
+ samsung,tzmp;
+
+ /* MFC version */
+ ip_ver = <0x1600010D>;
+
+ /* for F/W buffer */
+ fw-region = <&mfc_core1_mem>;
+
+ /* Sysmmu check */
+ share_sysmmu = <0>;
+ axid_mask = <0xFFFF>;
+
+ /* Device virtual address */
+ #dma-address-cells = <1>;
+ #dma-size-cells = <1>;
+ dma-window = <0x0 0xF0000000>;
+
+ /* Sub nodes for sysmmu, hwfc and mmcache */
+ iommu@...70000 {
+ reg = <0x0 0x19E70000 0x0 0x9000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index 0fdf2062930a..f35441d29cdd 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -1507,3 +1507,4 @@ timer {
};
#include "exynosautov920-pinctrl.dtsi"
+#include "exynosautov920-evt2-mfc.dtsi"
--
2.34.1
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