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Message-ID: <CACSVV01UygpiUj0m_Ppd_LSxvW0MFunz+Lfhg20XHR7vyOBx7w@mail.gmail.com>
Date: Tue, 30 Sep 2025 01:27:45 -0700
From: Rob Clark <rob.clark@....qualcomm.com>
To: Akhil P Oommen <akhilpo@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Sean Paul <sean@...rly.run>,
Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jessica.zhang@....qualcomm.com>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Jonathan Marek <jonathan@...ek.ca>,
Jordan Crouse <jordan@...micpenguin.net>,
Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>,
Joerg Roedel <joro@...tes.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-arm-kernel@...ts.infradead.org,
iommu@...ts.linux.dev, devicetree@...r.kernel.org
Subject: Re: [PATCH 13/17] drm/msm/adreno: Support AQE engine
On Mon, Sep 29, 2025 at 10:51 PM Akhil P Oommen
<akhilpo@....qualcomm.com> wrote:
>
> AQE (Applicaton Qrisc Engine) is a dedicated core inside CP which aides
> in Raytracing related workloads. Add support for loading the AQE firmware
> and initialize the necessary registers.
>
> Signed-off-by: Akhil P Oommen <akhilpo@....qualcomm.com>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 24 ++++++++++++++++++++++++
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 ++
> drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 3 +++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> 4 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 4aeeaceb1fb30a9d68ac636c14249e3853ef73ac..07ac5be9d0bccf4d2345eb76b08851a94187e861 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -1093,6 +1093,30 @@ static int a6xx_ucode_load(struct msm_gpu *gpu)
> }
> }
>
> + if (!a6xx_gpu->aqe_bo && adreno_gpu->fw[ADRENO_FW_AQE]) {
> + a6xx_gpu->aqe_bo = adreno_fw_create_bo(gpu,
> + adreno_gpu->fw[ADRENO_FW_AQE], &a6xx_gpu->aqe_iova);
> +
> + if (IS_ERR(a6xx_gpu->aqe_bo)) {
> + int ret = PTR_ERR(a6xx_gpu->aqe_bo);
> +
> + a6xx_gpu->aqe_bo = NULL;
> + DRM_DEV_ERROR(&gpu->pdev->dev,
> + "Could not allocate AQE ucode: %d\n", ret);
> +
> + return ret;
> + }
> +
> + msm_gem_object_set_name(a6xx_gpu->aqe_bo, "aqefw");
> + if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->aqe_bo)) {
a6xx_ucode_check_version() doesn't do anything for aqe fw (but also
a6xx_ucode_check_version() should probably bail early for a8xx at this
point?)
OTOH if over time we keep growing the version checks, we might need to
re-think how a6xx_ucode_check_version() works. But that is not a now
problem.
BR,
-R
> + msm_gem_unpin_iova(a6xx_gpu->aqe_bo, gpu->vm);
> + drm_gem_object_put(a6xx_gpu->aqe_bo);
> +
> + a6xx_gpu->aqe_bo = NULL;
> + return -EPERM;
> + }
> + }
> +
> /*
> * Expanded APRIV and targets that support WHERE_AM_I both need a
> * privileged buffer to store the RPTR shadow
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> index 18300b12bf2a8bcd5601797df0fcc7afa8943863..a6ef8381abe5dd3eb202a645bb87a3bc352df047 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> @@ -58,6 +58,8 @@ struct a6xx_gpu {
>
> struct drm_gem_object *sqe_bo;
> uint64_t sqe_iova;
> + struct drm_gem_object *aqe_bo;
> + uint64_t aqe_iova;
>
> struct msm_ringbuffer *cur_ring;
> struct msm_ringbuffer *next_ring;
> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> index 6a64b1f96d730a46301545c52a83d62dddc6c2ff..9a09ce37687aba2f720637ec3845a25d72d2fff7 100644
> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> @@ -599,6 +599,9 @@ static int hw_init(struct msm_gpu *gpu)
> goto out;
>
> gpu_write64(gpu, REG_A8XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova);
> + if (a6xx_gpu->aqe_iova)
> + gpu_write64(gpu, REG_A8XX_CP_AQE_INSTR_BASE_0, a6xx_gpu->aqe_iova);
> +
> /* Set the ringbuffer address */
> gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova);
> gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 6a2157f31122ba0c2f2a7005c98e3e4f1ada6acc..3de3a2cda7a1b9e6d4c32075afaadc6604e74b15 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -27,6 +27,7 @@ enum {
> ADRENO_FW_PFP = 1,
> ADRENO_FW_GMU = 1, /* a6xx */
> ADRENO_FW_GPMU = 2,
> + ADRENO_FW_AQE = 3,
> ADRENO_FW_MAX,
> };
>
>
> --
> 2.51.0
>
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