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Message-ID: <CAAT7Ki9_Vm0+v9RHpa2w-Bg3agJy2Tp4d6+tcPJ=M7XX3GV-7Q@mail.gmail.com>
Date: Wed, 8 Oct 2025 05:36:30 +0800
From: Han Gao <rabenda.cn@...il.com>
To: Alexandre Ghiti <alex@...ti.fr>
Cc: guoren@...nel.org, palmer@...belt.com, conor@...nel.org,
alexghiti@...osinc.com, paul.walmsley@...ive.com, bjorn@...osinc.com,
eobras@...hat.com, corbet@....net, peterlin@...estech.com,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Leonardo Bras <leobras@...hat.com>
Subject: Re: [PATCH V2 2/2] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup
Hi Alex
This patch is included in the 6.17 merge window but not in the
6.18 merge window.
Is it possible that the patch was missed?
On Thu, Jul 17, 2025 at 4:22 PM Alexandre Ghiti <alex@...ti.fr> wrote:
>
> On 7/13/25 17:53, guoren@...nel.org wrote:
> > From: "Guo Ren (Alibaba DAMO Academy)" <guoren@...nel.org>
> >
> > The early version of XuanTie C910 core has a store merge buffer
> > delay problem. The store merge buffer could improve the store queue
> > performance by merging multi-store requests, but when there are not
> > continued store requests, the prior single store request would be
> > waiting in the store queue for a long time. That would cause
> > significant problems for communication between multi-cores. This
> > problem was found on sg2042 & th1520 platforms with the qspinlock
> > lock torture test.
> >
> > So appending a fence w.o could immediately flush the store merge
> > buffer and let other cores see the write result.
> >
> > This will apply the WRITE_ONCE errata to handle the non-standard
> > behavior via appending a fence w.o instruction for WRITE_ONCE().
> >
> > This problem is only observed on the sg2042 hardware platform by
> > running the lock_torture test program for half an hour. The problem
> > was not found in the user space application, because interrupt can
> > break the livelock.
> >
> > Reviewed-by: Leonardo Bras <leobras@...hat.com>
> > Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@...nel.org>
> > ---
> > arch/riscv/Kconfig.errata | 17 ++++++++++
> > arch/riscv/errata/thead/errata.c | 20 ++++++++++++
> > arch/riscv/include/asm/errata_list_vendors.h | 3 +-
> > arch/riscv/include/asm/rwonce.h | 34 ++++++++++++++++++++
> > include/asm-generic/rwonce.h | 2 ++
> > 5 files changed, 75 insertions(+), 1 deletion(-)
> > create mode 100644 arch/riscv/include/asm/rwonce.h
> >
> > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > index e318119d570d..d2c982ba5373 100644
> > --- a/arch/riscv/Kconfig.errata
> > +++ b/arch/riscv/Kconfig.errata
> > @@ -130,4 +130,21 @@ config ERRATA_THEAD_GHOSTWRITE
> >
> > If you don't know what to do here, say "Y".
> >
> > +config ERRATA_THEAD_WRITE_ONCE
> > + bool "Apply T-Head WRITE_ONCE errata"
> > + depends on ERRATA_THEAD
> > + default y
> > + help
> > + The early version of T-Head C9xx cores of sg2042 & th1520 have a store
> > + merge buffer delay problem. The store merge buffer could improve the
> > + store queue performance by merging multi-store requests, but when there
> > + are no continued store requests, the prior single store request would be
> > + waiting in the store queue for a long time. That would cause signifi-
> > + cant problems for communication between multi-cores. Appending a
> > + fence w.o could immediately flush the store merge buffer and let other
> > + cores see the write result.
> > +
> > + This will apply the WRITE_ONCE errata to handle the non-standard beh-
> > + avior via appending a fence w.o instruction for WRITE_ONCE().
> > +
> > endmenu # "CPU errata selection"
> > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > index 0b942183f708..fbe46f2fa8fb 100644
> > --- a/arch/riscv/errata/thead/errata.c
> > +++ b/arch/riscv/errata/thead/errata.c
> > @@ -168,6 +168,23 @@ static bool errata_probe_ghostwrite(unsigned int stage,
> > return true;
> > }
> >
> > +static bool errata_probe_write_once(unsigned int stage,
> > + unsigned long arch_id, unsigned long impid)
> > +{
> > + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE))
> > + return false;
> > +
> > + /* target-c9xx cores report arch_id and impid as 0 */
> > + if (arch_id != 0 || impid != 0)
> > + return false;
> > +
> > + if (stage == RISCV_ALTERNATIVES_BOOT ||
> > + stage == RISCV_ALTERNATIVES_MODULE)
> > + return true;
> > +
> > + return false;
> > +}
> > +
> > static u32 thead_errata_probe(unsigned int stage,
> > unsigned long archid, unsigned long impid)
> > {
> > @@ -183,6 +200,9 @@ static u32 thead_errata_probe(unsigned int stage,
> >
> > errata_probe_ghostwrite(stage, archid, impid);
> >
> > + if (errata_probe_write_once(stage, archid, impid))
> > + cpu_req_errata |= BIT(ERRATA_THEAD_WRITE_ONCE);
> > +
> > return cpu_req_errata;
> > }
> >
> > diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h
> > index a37d1558f39f..a7473cb8874d 100644
> > --- a/arch/riscv/include/asm/errata_list_vendors.h
> > +++ b/arch/riscv/include/asm/errata_list_vendors.h
> > @@ -18,7 +18,8 @@
> > #define ERRATA_THEAD_MAE 0
> > #define ERRATA_THEAD_PMU 1
> > #define ERRATA_THEAD_GHOSTWRITE 2
> > -#define ERRATA_THEAD_NUMBER 3
> > +#define ERRATA_THEAD_WRITE_ONCE 3
> > +#define ERRATA_THEAD_NUMBER 4
> > #endif
> >
> > #endif
> > diff --git a/arch/riscv/include/asm/rwonce.h b/arch/riscv/include/asm/rwonce.h
> > new file mode 100644
> > index 000000000000..081793d4d772
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/rwonce.h
> > @@ -0,0 +1,34 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +
> > +#ifndef __ASM_RWONCE_H
> > +#define __ASM_RWONCE_H
> > +
> > +#include <linux/compiler_types.h>
> > +#include <asm/alternative-macros.h>
> > +#include <asm/vendorid_list.h>
> > +#include <asm/errata_list_vendors.h>
> > +
> > +#if defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE)
> > +
> > +#define write_once_fence() \
> > +do { \
> > + asm volatile(ALTERNATIVE( \
> > + "nop", \
> > + "fence w, o", \
> > + THEAD_VENDOR_ID, \
> > + ERRATA_THEAD_WRITE_ONCE, \
> > + CONFIG_ERRATA_THEAD_WRITE_ONCE) \
> > + : : : "memory"); \
> > +} while (0)
> > +
> > +#define __WRITE_ONCE(x, val) \
> > +do { \
> > + *(volatile typeof(x) *)&(x) = (val); \
> > + write_once_fence(); \
> > +} while (0)
> > +
> > +#endif /* defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) */
> > +
> > +#include <asm-generic/rwonce.h>
> > +
> > +#endif /* __ASM_RWONCE_H */
> > diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h
> > index 52b969c7cef9..4e2d941f15a1 100644
> > --- a/include/asm-generic/rwonce.h
> > +++ b/include/asm-generic/rwonce.h
> > @@ -50,10 +50,12 @@
> > __READ_ONCE(x); \
> > })
> >
> > +#ifndef __WRITE_ONCE
> > #define __WRITE_ONCE(x, val) \
> > do { \
> > *(volatile typeof(x) *)&(x) = (val); \
> > } while (0)
> > +#endif
> >
> > #define WRITE_ONCE(x, val) \
> > do { \
>
> I'll send this patchset in my next PR for 6.17:
>
> Reviewed-by: Alexandre Ghiti <alexghiti@...osinc.com>
>
> Thanks,
>
> Alex
>
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