linux-kernel - Re: [PATCH V2 0/2] riscv: errata: Add ERRATA_THEAD_WRITE

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Message-Id: 
 <175450054624.2863135.16531031076393006761.git-patchwork-notify@kernel.org>
Date: Wed, 06 Aug 2025 17:15:46 +0000
From: patchwork-bot+linux-riscv@...nel.org
To: Guo Ren <guoren@...nel.org>
Cc: linux-riscv@...ts.infradead.org, palmer@...belt.com, conor@...nel.org,
 alexghiti@...osinc.com, paul.walmsley@...ive.com, bjorn@...osinc.com,
 eobras@...hat.com, corbet@....net, peterlin@...estech.com,
 rabenda.cn@...il.com, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2 0/2] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup

Hello:

This series was applied to riscv/linux.git (for-next)
by Alexandre Ghiti <alexghiti@...osinc.com>:

On Sun, 13 Jul 2025 11:53:19 -0400 you wrote:
> From: "Guo Ren (Alibaba DAMO Academy)" <guoren@...nel.org>
> 
> The early version of XuanTie C9xx cores has a store merge buffer
> delay problem. The store merge buffer could improve the store queue
> performance by merging multi-store requests, but when there are not
> continued store requests, the prior single store request would be
> waiting in the store queue for a long time. That would cause
> significant problems for communication between multi-cores. This
> problem was found on sg2042 & th1520 platforms with the qspinlock
> lock torture test.
> 
> [...]

Here is the summary with links:
  - [V2,1/2] riscv: Move vendor errata definitions to new header
    https://git.kernel.org/riscv/c/736d67e4f0d0
  - [V2,2/2] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup
    https://git.kernel.org/riscv/c/b7f09bd30ca8

You are awesome, thank you!
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