[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <ea85d388-c0c1-4b4a-96d6-d3f27622ed54@kernel.org>
Date: Tue, 7 Oct 2025 15:32:48 +0900
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Sanghoon Bae <sh86.bae@...sung.com>, robh@...nel.org,
conor+dt@...nel.org, vkoul@...nel.org, alim.akhtar@...sung.com,
kishon@...nel.org, m.szyprowski@...sung.com, jh80.chung@...sung.com,
shradha.t@...sung.com
Cc: krzk+dt@...nel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-samsung-soc@...r.kernel.org,
linux-phy@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 3/4] arm64: dts: ExynosAutov920: add PCIe PHY DT nodes
On 26/09/2025 16:39, Sanghoon Bae wrote:
> Add pcie_4l_phy, pcie_2l_phy dt node for all PCIe PHY instances
> in ExynosAutov920 SoC.
>
> Add HSI sysreg to control PCIe sysreg registers.
>
> Signed-off-by: Sanghoon Bae <sh86.bae@...sung.com>
> ---
> .../arm64/boot/dts/exynos/exynosautov920.dtsi | 28 +++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> index 2cb8041c8a9f..9e45bfcd7980 100644
> --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> @@ -1021,12 +1021,40 @@ cmu_hsi0: clock-controller@...00000 {
> "noc";
> };
>
> + syscon_hsi0: syscon@...30000 {
> + compatible = "samsung,exynosautov920-hsi0-sysreg",
> + "syscon";
> + reg = <0x16030000 0x1000>;
> + };
> +
> pinctrl_hsi0: pinctrl@...40000 {
> compatible = "samsung,exynosautov920-pinctrl";
> reg = <0x16040000 0x10000>;
> interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + pcie_2l_phy: pcie-phy2l@...c6000{
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
If you cannot find a name matching your device, please check in kernel
sources for similar cases or you can grow the spec (via pull request to
DT spec repo).
Plus style issues... missing space.
I would like to see also PCIe nodes somewhere, because I wonder if
num-lanes should not be moved to PCI node (phy consumer) instead.
Current approach feels better, but maybe it just duplicates num-lanes
from the PCI?
Best regards,
Krzysztof
Powered by blists - more mailing lists