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Message-ID: <923aea1b-6a15-426f-9c32-954a1fb95d0a@kernel.org>
Date: Tue, 7 Oct 2025 09:42:24 +0900
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Roy Luo <royluo@...gle.com>, Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Peter Griffin <peter.griffin@...aro.org>,
André Draszik <andre.draszik@...aro.org>,
Tudor Ambarus <tudor.ambarus@...aro.org>
Cc: Joy Chakraborty <joychakr@...gle.com>, Naveen Kumar <mnkumar@...gle.com>,
linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-usb@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH v1 3/4] usb: dwc3: Add Google SoC USB PHY driver
On 07/10/2025 08:21, Roy Luo wrote:
> Support the USB PHY found on Google Tensor SoCs.
> This particular USB PHY supports both high-speed and super-speed
> operations, and is paired with the SNPS DWC3 controller that's also
> integrated on the SoCs.
> This initial patch specifically adds functionality for high-speed.
>
> Co-developed-by: Joy Chakraborty <joychakr@...gle.com>
> Signed-off-by: Joy Chakraborty <joychakr@...gle.com>
> Co-developed-by: Naveen Kumar <mnkumar@...gle.com>
> Signed-off-by: Naveen Kumar <mnkumar@...gle.com>
> Signed-off-by: Roy Luo <royluo@...gle.com>
> ---
> drivers/phy/Kconfig | 1 +
> drivers/phy/Makefile | 1 +
> drivers/phy/google/Kconfig | 15 ++
> drivers/phy/google/Makefile | 2 +
> drivers/phy/google/phy-google-usb.c | 286 ++++++++++++++++++++++++++++
No, you don't get a new directory and new driver. That's a Samsung part,
AFAIK. Re-use existing code.
Best regards,
Krzysztof
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