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Message-ID: <91da537e-01ea-4b51-8493-8cf88d64b435@nvidia.com>
Date: Tue, 7 Oct 2025 15:50:56 +0100
From: Jon Hunter <jonathanh@...dia.com>
To: Akhil R <akhilrajeev@...dia.com>, andi.shyti@...nel.org,
conor+dt@...nel.org, devicetree@...r.kernel.org, digetx@...il.com,
krzk+dt@...nel.org, linux-i2c@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-tegra@...r.kernel.org
Cc: ldewangan@...dia.com, robh@...nel.org, thierry.reding@...il.com,
Thierry Reding <treding@...dia.com>
Subject: Re: [PATCH RESEND 2/2] i2c: tegra: Add Tegra256 support
Hi Akhil,
On 18/08/2025 05:33, Akhil R wrote:
> Add compatible and the hardware struct for Tegra256. Tegra256 controllers
> use a different parent clock. Hence the timing parameters are different
> from the previous generations to meet the expected frequencies.
>
> Signed-off-by: Akhil R <akhilrajeev@...dia.com>
> Acked-by: Thierry Reding <treding@...dia.com>
>
> ---
> drivers/i2c/busses/i2c-tegra.c | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> index 4eb31b913c1a..e533460bccc3 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c
> @@ -1649,7 +1649,33 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
> .has_interface_timing_reg = true,
> };
>
> +static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
> + .has_continue_xfer_support = true,
> + .has_per_pkt_xfer_complete_irq = true,
> + .clk_divisor_hs_mode = 7,
> + .clk_divisor_std_mode = 0x7a,
> + .clk_divisor_fast_mode = 0x40,
> + .clk_divisor_fast_plus_mode = 0x19,
Can you check this divisor value? I see we have been using a value of
0x14 for this which does not align with what we have here. Can you
confirm if this should be 0x19 or 0x14?
Thanks
Jon
--
nvpublic
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