Message-ID: <0f5f2793-13d6-416e-ad0e-1840e22b753c@ixit.cz>
Date: Thu, 9 Oct 2025 23:20:49 +0200
From: David Heidelberg <david@...t.cz>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
 Konrad Dybcio <konradybcio@...nel.org>
Cc: Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 Amit Pundir <amit.pundir@...aro.org>, Casey Connolly <casey@...nolly.tech>,
 Joel Selvaraj <foss@...lselvaraj.com>, Sumit Semwal
 <sumit.semwal@...aro.org>, Vinod Koul <vkoul@...nel.org>
Subject: Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3
 XL

On 06/10/2025 00:03, Dmitry Baryshkov wrote:
> On Sun, Oct 05, 2025 at 03:16:29PM +0200, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@...t.cz>
>>
>> This adds initial device tree support for the following phones:
>>
>>   - Google Pixel 3 (blueline)
>>   - Google Pixel 3 XL (crosshatch)
> 
> Great to finally see it being submitted!
> 
>>
>> Both phone boards use the same identifiers and differ only slightly
>> in their connected peripherals.
>>
>> Supported functionality includes:
>>   - Debug UART
>>   - UFS
>>   - Charger
>>   - USB-C (peripheral mode)
>>   - Display (Pixel 3 only)
> 
> No remoteprocs / IPA / GPU / Venus / WiFi / BT? The firmware is
> accessible to download from Google and it can be further repackaged (but
> not redistributed). See [1], [2].

Since I didn't have Pixel 3 at hand to test (I sent the series when 
attending event where someone had Pixel 3 ;-) ), I was aiming to merge 
MVP.. more precisely, Minimal Viable Device-tree (MVD).

Until the end of the month I should have also Pixel 3, so I'll 
definitely continue to enable all the mentioned features, but as this 
DTB is also needed for u-boot [1], I would prefer to get MVD in ASAP, 
mostly because of the fastboot is useless for loading mainline kernel.

[1] https://gitlab.postmarketos.org/tauchgang

Before I'll send the v2, the progress can be tracked in
   https://gitlab.com/dhxx/linux/-/commits/b4/pixel-3

Thank you both for the review!
David

> 
> The phones share all firmware except for the bdwlan, so hopefully you
> can add 'Google/blueline/foo.mbn' to the common file.
> 
> [1] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel3.bb
> [2] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel.inc
> 
>>
>> GPIOs 0–3 and 81–84 are not accessible from the application CPUs,
>> so they are marked as reserved to allow the Pixel 3 to boot.
>>
>> The rmtfs region is allocated using UIO, making it technically "dynamic."
>>
>> Its address and size can be read from sysfs:
>>
>> $ cat /sys/class/uio/uio0/name
>> /sys/class/uio/uio0/maps/map0/addr
>> 0x00000000f2701000
>>
>> $ cat /sys/class/uio/uio0/maps/map0/size
>> 0x0000000000200000
>>
>> Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either
>> side of the rmtfs region to work around an XPU bug that would otherwise
>> cause erroneous violations when accessing the rmtfs_mem region.
>>
>> Co-developed-by: Amit Pundir <amit.pundir@...aro.org>
>> Signed-off-by: Amit Pundir <amit.pundir@...aro.org>
>> Co-developed-by: Bjorn Andersson <bjorn.andersson@...aro.org>
>> Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>
>> Co-developed-by: Casey Connolly <casey@...nolly.tech>
>> Signed-off-by: Casey Connolly <casey@...nolly.tech>
>> Co-developed-by: Joel Selvaraj <foss@...lselvaraj.com>
>> Signed-off-by: Joel Selvaraj <foss@...lselvaraj.com>
>> Co-developed-by: Sumit Semwal <sumit.semwal@...aro.org>
>> Signed-off-by: Sumit Semwal <sumit.semwal@...aro.org>
>> Co-developed-by: Vinod Koul <vkoul@...nel.org>
>> Signed-off-by: Vinod Koul <vkoul@...nel.org>
>> Signed-off-by: David Heidelberg <david@...t.cz>
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile                  |   2 +
>>   .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 128 ++++++
>>   arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 467 +++++++++++++++++++++
>>   .../boot/dts/qcom/sdm845-google-crosshatch.dts     | 137 ++++++
>>   4 files changed, 734 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 4bfa926b6a085..ba05dc935dc7c 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -239,6 +239,8 @@ dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-db845c.dtb
>>   sdm845-db845c-navigation-mezzanine-dtbs	:= sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
>>   
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-db845c-navigation-mezzanine.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-google-crosshatch.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-google-blueline.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-lg-judyln.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-lg-judyp.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-mtp.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
>> new file mode 100644
>> index 0000000000000..df88982018b9e
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
>> @@ -0,0 +1,128 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +
>> +/dts-v1/;
>> +
>> +#include "sdm845-google-common.dtsi"
>> +
>> +/ {
>> +	model = "Google Pixel 3";
>> +	compatible = "google,blueline", "qcom,sdm845";
>> +
>> +	battery: battery {
>> +		compatible = "simple-battery";
>> +
>> +		charge-full-design-microamp-hours = <2970000>;
>> +		voltage-min-design-microvolt = <3600000>;
>> +		voltage-max-design-microvolt = <4400000>;
>> +	};
>> +
>> +	chosen {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		/* for u-boot */
>> +		framebuffer: framebuffer@...00000 {
>> +			compatible = "simple-framebuffer";
>> +			reg = <0 0x9d400000 0 (2160 * 1080 * 4)>;
>> +			width = <1080>;
>> +			height = <2160>;
>> +			stride = <(1080 * 4)>;
>> +			format = "a8r8g8b8";
>> +		};
>> +	};
>> +
>> +	reserved-memory {
>> +		framebuffer_region@...00000 {
> 
> Can't we use cont_splash_mem and let bootloader set it?
> 
>> +			no-map;
>> +			reg = <0 0x9d400000 0 0x02400000>; // FIXME
>> +		};
>> +	};
>> +};
>> +
>> +&gmu {
>> +	status = "okay";
>> +};
> 
> No need to, it's enabled by default.
> 
>> +
>> +&mdss {
>> +	status = "okay";
>> +};
>> +
>> +&mdss_dsi0 {
>> +	status = "okay";
>> +	vdda-supply = <&vdda_mipi_dsi0_1p2>;
>> +
>> +	ports {
>> +		port@1 {
>> +			endpoint {
>> +				remote-endpoint = <&panel_in>;
>> +				data-lanes = <0 1 2 3>;
>> +				qcom,te-source = "mdp_vsync_e";
> 
> &mdss_dsi1_out {
> 	remote-endpoint = <&panel_in>;
> 	.....
> };
> 
> 
>> +			};
>> +		};
>> +	};
>> +
>> +	panel@0 {
>> +		compatible = "lg,sw43408";
>> +		reg = <0>;
>> +
>> +		vddi-supply = <&vreg_l14a_1p88>;
>> +		vpnl-supply = <&vreg_l28a_3p0>;
>> +
>> +		reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
>> +
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>;
>> +
>> +		port {
>> +			panel_in: endpoint {
>> +				remote-endpoint = <&mdss_dsi0_out>;
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&mdss_dsi0_out {
>> +	remote-endpoint = <&panel_in>;
>> +	data-lanes = <0 1 2 3>;
>> +};
>> +
>> +&mdss_dsi0_phy {
>> +	vdds-supply = <&vdda_mipi_dsi0_pll>;
>> +
>> +	status = "okay";
>> +};
>> +
>> +&pm8998_gpios {
>> +	panel_pmgpio_pins: panel-pmgpio-active-state {
> 
> Are these two actually used by the panel? I think they were only used
> for sw43402, but not for sw43408.
> 
>> +		pins = "gpio2", "gpio5";
>> +		function = "normal";
>> +		input-enable;
>> +		bias-disable;
>> +		power-source = <0>;
>> +	};
>> +};
>> +
>> +
>> +	volume-keys {
> 
> gpio-keys ?
> 
>> +		compatible = "gpio-keys";
>> +		label = "Volume keys";
>> +		autorepeat;
>> +
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&volume_up_gpio>;
>> +
>> +		key-vol-up {
>> +			label = "Volume Up";
>> +			linux,code = <KEY_VOLUMEUP>;
>> +			gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
>> +			debounce-interval = <15>;
>> +		};
>> +	};
>> +
>> +	vph_pwr: vph-pwr-regulator {
> 
> Nit: BCP is regulator-foo-bar
> 
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "vph_pwr";
>> +		regulator-min-microvolt = <3700000>;
>> +		regulator-max-microvolt = <3700000>;
>> +	};
>> +
>> +	vreg_s4a_1p8: vreg-s4a-1p8-regulator {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "vreg_s4a_1p8";
>> +
>> +		regulator-min-microvolt = <1800000>;
>> +		regulator-max-microvolt = <1800000>;
>> +		regulator-always-on;
>> +		regulator-boot-on;
>> +
>> +		vin-supply = <&vph_pwr>;
>> +	};
>> +};
>> +
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
>> new file mode 100644
>> index 0000000000000..dc9938ffc0ab8
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
>> @@ -0,0 +1,137 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +
>> +/dts-v1/;
>> +
>> +#include "sdm845-google-common.dtsi"
>> +
>> +/ {
>> +	model = "Google Pixel 3 XL";
>> +	compatible = "google,crosshatch", "qcom,sdm845";
>> +
>> +	battery: battery {
>> +		compatible = "simple-battery";
>> +
>> +		charge-full-design-microamp-hours = <3480000>;
>> +		voltage-min-design-microvolt = <3600000>;
>> +		voltage-max-design-microvolt = <4400000>;
>> +	};
>> +
>> +	chosen {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
> 
> These are all the same as the -blueline. Please move common options to
> the -common.dtsi
> 
>> +
>> +		/* for u-boot */
>> +		framebuffer: framebuffer@...00000 {
>> +			compatible = "simple-framebuffer";
>> +			reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;
>> +			width = <1440>;
>> +			height = <2960>;
>> +			stride = <(1440 * 4)>;
>> +			format = "a8r8g8b8";
>> +		};
>> +	};
>> +
>> +	reserved-memory {
>> +		framebuffer_region@...00000 {
>> +			no-map;
>> +			reg = <0 0x9d400000 0 0x02400000>;
>> +		};
>> +	};
>> +};
>> +
>> +&gmu {
>> +	status = "okay";
>> +};
>> +
>> +&mdss {
> 
> More and more common properties. Please move them to the common file.

Sorry about this, the mdss nodes got in by accident, the display driver 
for crosshatch is WIP.>
>> +	status = "okay";
>> +};
>> +
>> +&mdss_dsi0 {
>> +	vdda-supply = <&vdda_mipi_dsi0_1p2>;
>> +
>> +	status = "okay";
>> +
>> +	ports {
>> +		port@1 {
>> +			endpoint {
>> +				remote-endpoint = <&panel_in>;
>> +				data-lanes = <0 1 2 3>;
>> +				qcom,te-source = "mdp_vsync_e";
>> +			};
>> +		};
>> +	};
>> +
>> +	panel@0 {
>> +		compatible = "samsung,s6e3ha8";
>> +		reg = <0>;
>> +
>> +		vci-supply = <&vreg_l28a_3p0>; // downstream
>> +		vdd3-supply = <&vreg_l28a_3p0>;
>> +		vddr-supply = <&vreg_l14a_1p88>;
>> +
>> +		reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
>> +
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&panel_reset_pins &panel_te_pin &se8_spiflash &panel_pmgpio_pins>;
> 
> - Why do you need spiflash here?
> - I don't think this uses pmgpios too.
> 
>> +
>> +		port {
>> +			panel_in: endpoint {
>> +				remote-endpoint = <&mdss_dsi0_out>;
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&mdss_dsi0_out {
>> +	data-lanes = <0 1 2 3>;
>> +	remote-endpoint = <&panel_in>;
>> +};
>> +
>> +&mdss_dsi0_phy {
>> +	vdds-supply = <&vdda_mipi_dsi0_pll>;
>> +
>> +	status = "okay";
>> +};
>> +
>> +&pm8998_gpios {
>> +	panel_pmgpio_pins: panel-pmgpio-active-state {
>> +		pins = "gpio2", "gpio5";
>> +		function = "normal";
>> +		input-enable;
>> +		bias-disable;
>> +		power-source = <0>;
>> +	};
>> +};
>> +
>> +&tlmm {
>> +	se8_spiflash: se8-spiflash-state {
>> +		pins = "gpio65", "gpio66", "gpio67", "gpio68";
>> +		function = "gpio";
>> +		input-enable;
>> +		bias-disable;
>> +	};
>> +
>> +	panel_te_pin: panel-te-state {
>> +		pins = "gpio12";
>> +		function = "mdp_vsync";
>> +		drive-strength = <2>;
>> +		bias-pull-down;
>> +	};
>> +
>> +	panel_reset_pins: panel-active-state {
>> +		pins = "gpio6";
>> +		function = "gpio";
>> +		drive-strength = <8>;
>> +		bias-disable;
>> +	};
>> +
>> +	panel_suspend: panel-suspend-state {
>> +		pins = "gpio6";
>> +		function = "gpio";
>> +		drive-strength = <2>;
>> +		bias-pull-down;
>> +	};
>> +
>> +};
>>
>> -- 
>> 2.51.0
>>
>>
> 

-- 
David Heidelberg

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