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Message-ID: <CA+zupgxnBK_k2X0_KKX9pUMMTwY4VhsyTEEVz6v+__u=2xR8Ow@mail.gmail.com>
Date: Wed, 8 Oct 2025 21:40:57 -0700
From: Roy Luo <royluo@...gle.com>
To: Conor Dooley <conor@...nel.org>
Cc: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
Philipp Zabel <p.zabel@...gutronix.de>, Peter Griffin <peter.griffin@...aro.org>,
André Draszik <andre.draszik@...aro.org>,
Tudor Ambarus <tudor.ambarus@...aro.org>, Joy Chakraborty <joychakr@...gle.com>,
Naveen Kumar <mnkumar@...gle.com>, Badhri Jagan Sridharan <badhri@...gle.com>, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-usb@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH v2 1/4] dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3
On Wed, Oct 8, 2025 at 1:58 PM Conor Dooley <conor@...nel.org> wrote:
>
> On Wed, Oct 08, 2025 at 05:59:57AM +0000, Roy Luo wrote:
> > Document the device tree bindings for the DWC3 USB controller found in
> > Google Tensor SoCs, starting with the G5 generation.
> >
> > The Tensor G5 silicon represents a complete architectural departure from
> > previous generations (like gs101), including entirely new clock/reset
> > schemes, top-level wrapper and register interface. Consequently,
> > existing Samsung/Exynos DWC3 USB bindings and drivers are incompatible,
> > necessitating this new device tree binding.
> >
> > The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features
> > Dual-Role Device single port with hibernation support.
> >
> > Signed-off-by: Roy Luo <royluo@...gle.com>
> > ---
> > .../bindings/usb/google,gs-dwc3.yaml | 145 ++++++++++++++++++
> > 1 file changed, 145 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml
> > new file mode 100644
> > index 000000000000..9eb0bf726e8d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml
>
> filename matching the compatible please.
>
> > @@ -0,0 +1,145 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +# Copyright (c) 2025, Google LLC
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/usb/google,gs-dwc3.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Google Tensor Series (G5+) DWC3 USB SoC Controller
> > +
> > +maintainers:
> > + - Roy Luo <royluo@...gle.com>
> > +
> > +description: |
> > + Describes the DWC3 USB controller block implemented on Google Tensor SoCs,
> > + starting with the G5 generation. Based on Synopsys DWC3 IP, the controller
> > + features Dual-Role Device single port with hibernation add-on.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - google,gs5-dwc3
>
> items is redundant here.
>
> > +
> > + reg:
> > + minItems: 3
> > + maxItems: 3
> > +
> > + reg-names:
> > + description: |
> > + The following memory regions must present:
> > + - dwc3_core: Core DWC3 IP registers.
> > + - host_cfg_csr: Hibernation control registers.
> > + - usbint_csr: Hibernation interrupt registers.
>
> Put this into reg as an items list, and you can drop the min/max items
> from there.
> Same applies to interrupts and power-domains.
>
> > + items:
> > + - const: dwc3_core
> > + - const: host_cfg_csr
> > + - const: usbint_csr
> > +
> > + interrupts:
> > + minItems: 3
> > + maxItems: 3
> > +
> > + interrupt-names:
> > + description: |
> > + The following interrupts must present:
> > + - dwc_usb3: Core DWC3 interrupt.
> > + - hs_pme_irq: High speed remote wakeup interrupt for hibernation.
> > + - ss_pme_irq: Super speed remote wakeup interrupt for hibernation.
> > + items:
> > + - const: dwc_usb3
> > + - const: hs_pme_irq
> > + - const: ss_pme_irq
>
> s/_irq//
>
> > +
> > + clocks:
> > + minItems: 3
> > + maxItems: 3
> > +
> > + clock-names:
> > + minItems: 3
> > + maxItems: 3
> > +
> > + resets:
> > + minItems: 5
> > + maxItems: 5
>
> For clocks and resets, please provide descriptions. For clock-names, you
> provided no names and therefore cannot use the property since anything
> is valid!
>
> > +
> > + reset-names:
> > + items:
> > + - const: usbc_non_sticky
> > + - const: usbc_sticky
> > + - const: usb_drd_bus
> > + - const: u2phy_apb
> > + - const: usb_top_csr
>
> "csr" is an odd thing to have in a reset name, since it usually means
> "control and status register". Why is it here.
>
> > +
> > + power-domains:
> > + minItems: 2
> > + maxItems: 2
> > +
> > + power-domain-names:
> > + description: |
> > + The following power domain must present:
> > + - usb_psw_pd: The child power domain of usb_top_pd. Turning it on puts the controller
> > + into full power state, turning it off puts the controller into power
> > + gated state.
> > + - usb_top_pd: The parent power domain of usb_psw_pd. Turning it on puts the controller
> > + into power gated state, turning it off completely shuts off the
> > + controller.
> > + items:
> > + - const: usb_psw_pd
> > + - const: usb_top_pd
>
> s/_pd// at the very least, but I would question the need to put "usb" in
> any of the names given that this is a usb device.
>
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - interrupts
> > + - interrupt-names
> > + - clocks
> > + - resets
> > + - reset-names
> > + - power-domains
> > + - power-domain-names
> > +
> > +allOf:
> > + - $ref: snps,dwc3-common.yaml#
> > +
> > +unevaluatedProperties: false
>
> So every property from snps,dwc3-common.yaml is valid here, with any of
> the permitted values?
Conor,
Appreciate the review.
Ack to all the comments, will fix them in the next patch.
And yes, every property from snps,dwc3-common.yaml is valid here.
You can find more context here [1], essentially the dwc3 glue would be
operating on the same platform device as the dwc3 core, hence all
properties are allowed.
[1] https://lore.kernel.org/all/20250414-dwc3-refactor-v7-0-f015b358722d@oss.qualcomm.com/
Thanks,
Roy Luo
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + usb@...0000 {
> > + compatible = "google,gs5-dwc3";
> > + reg = <0 0x0c400000 0 0xd060>, <0 0x0c450000 0 0x14>, <0 0x0c450020 0 0x8>;
> > + reg-names = "dwc3_core", "host_cfg_csr", "usbint_csr";
> > + interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH 0>,
> > + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,
> > + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>;
> > + interrupt-names = "dwc_usb3", "hs_pme_irq", "ss_pme_irq";
> > + clocks = <&hsion_usbc_non_sticky_clk>, <&hsion_usbc_sticky_clk>,
> > + <&hsion_u2phy_apb_clk>;
> > + clock-names = "usbc_non_sticky", "usbc_sticky", "u2phy_apb";
> > + resets = <&hsion_resets_usbc_non_sticky>, <&hsion_resets_usbc_sticky>,
> > + <&hsion_resets_usb_drd_bus>, <&hsion_resets_u2phy_apb>,
> > + <&hsion_resets_usb_top_csr>;
> > + reset-names = "usbc_non_sticky", "usbc_sticky",
> > + "usb_drd_bus", "u2phy_apb",
> > + "usb_top_csr";
> > + power-domains = <&hsio_n_usb_psw_pd>, <&hsio_n_usb_pd>;
> > + power-domain-names = "usb_psw_pd", "usb_top_pd";
> > + phys = <&usb_phy 0>;
> > + phy-names = "usb2-phy";
> > + snps,quirk-frame-length-adjustment = <0x20>;
> > + snps,gfladj-refclk-lpm-sel-quirk;
> > + snps,incr-burst-type-adjustment = <4>;
> > + };
> > + };
> > +...
>
> pw-bot: cr
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