linux-kernel - Re: [PATCH] RISC-V: KVM: flush VS-stage TLB after VCPU migration to prevent stale entries

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Message-Id: <DDDKX1VNCCVS.2KVYNU4WBEOVI@ventanamicro.com>
Date: Thu, 09 Oct 2025 08:31:41 +0200
From: Radim Krčmář <rkrcmar@...tanamicro.com>
To: "Ben Zong-You Xie" <ben717@...estech.com>
Cc: <anup@...infault.org>, <atish.patra@...ux.dev>, <pjw@...nel.org>,
 <palmer@...belt.com>, <aou@...s.berkeley.edu>, <alex@...ti.fr>,
 <liujingqi@...xincomputing.com>, <kvm@...r.kernel.org>,
 <kvm-riscv@...ts.infradead.org>, <linux-riscv@...ts.infradead.org>,
 <linux-kernel@...r.kernel.org>, <tim609@...estech.com>, "Hui Min Mina Chou"
 <minachou@...estech.com>, "linux-riscv"
 <linux-riscv-bounces@...ts.infradead.org>
Subject: Re: [PATCH] RISC-V: KVM: flush VS-stage TLB after VCPU migration to
 prevent stale entries

2025-10-02T11:34:02+08:00, Ben Zong-You Xie <ben717@...estech.com>:
> From: Hui Min Mina Chou <minachou@...estech.com>
>
> If multiple VCPUs of the same Guest/VM run on the same Host CPU,
> hfence.vvma only flushes that Host CPU’s VS-stage TLB. Other Host CPUs
> may retain stale VS-stage entries. When a VCPU later migrates to a
> different Host CPU, it can hit these stale GVA to GPA mappings, causing
> unexpected faults in the Guest.

The issue can also be hit with a single VCPU migrated over two harts:

  1) [hart A] accessing X as Y, caching X->Y in first stage TLB
  2) [hart B] remapping X to Z, sfence.vma
  3) [hart A] accessing X as Y, instead of correct Z

Migration from 2 to 1 does hfence.gvma, but that doesn't flush first
stage TLB, so the translation produces an error due to stale entries.

What RISC-V implementation are you using?  (And does the implementation
have the same memory access performance in V=0 and V=1 modes, even
though the latter has two levels of TLBs?)

> To fix this, kvm_riscv_gstage_vmid_sanitize() is extended to flush both
> G-stage and VS-stage TLBs whenever a VCPU migrates to a different Host CPU.
> This ensures that no stale VS-stage mappings remain after VCPU migration.
>
> Fixes: b79bf2025dbc ("RISC-V: KVM: Rename and move kvm_riscv_local_tlb_sanitize()")

b79bf2025dbc does not change behavior.
The bug must have been introduced earlier.

> Signed-off-by: Hui Min Mina Chou <minachou@...estech.com>
> Signed-off-by: Ben Zong-You Xie <ben717@...estech.com>
> ---
> diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c
> @@ -146,4 +146,10 @@ void kvm_riscv_gstage_vmid_sanitize(struct kvm_vcpu *vcpu)

The function is now doing more that sanitizing gstage.
Maybe we can again call it kvm_riscv_local_tlb_sanitize()?

>  
>  	vmid = READ_ONCE(vcpu->kvm->arch.vmid.vmid);
>  	kvm_riscv_local_hfence_gvma_vmid_all(vmid);
> +
> +	/*
> +	 * Flush VS-stage TLBs entry after VCPU migration to avoid using
> +	 * stale entries.
> +	 */
> +	kvm_riscv_local_hfence_vvma_all(vmid);
>  }

I had some nits, but the approach is sound,

Reviewed-by: Radim Krčmář <rkrcmar@...tanamicro.com>

Thanks.

---
There is a room for a RISC-V extension that tells whether the two TLB
flushes are needed, or hfence.gvma is enough. :)