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Message-ID: <20251002033402.610651-1-ben717@andestech.com>
Date: Thu, 2 Oct 2025 11:34:02 +0800
From: Ben Zong-You Xie <ben717@...estech.com>
To:
CC: <anup@...infault.org>, <atish.patra@...ux.dev>, <pjw@...nel.org>,
<palmer@...belt.com>, <aou@...s.berkeley.edu>, <alex@...ti.fr>,
<liujingqi@...xincomputing.com>, <kvm@...r.kernel.org>,
<kvm-riscv@...ts.infradead.org>, <linux-riscv@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <tim609@...estech.com>,
Hui Min Mina Chou
<minachou@...estech.com>,
Ben Zong-You Xie <ben717@...estech.com>
Subject: [PATCH] RISC-V: KVM: flush VS-stage TLB after VCPU migration to prevent stale entries
From: Hui Min Mina Chou <minachou@...estech.com>
If multiple VCPUs of the same Guest/VM run on the same Host CPU,
hfence.vvma only flushes that Host CPU’s VS-stage TLB. Other Host CPUs
may retain stale VS-stage entries. When a VCPU later migrates to a
different Host CPU, it can hit these stale GVA to GPA mappings, causing
unexpected faults in the Guest.
To fix this, kvm_riscv_gstage_vmid_sanitize() is extended to flush both
G-stage and VS-stage TLBs whenever a VCPU migrates to a different Host CPU.
This ensures that no stale VS-stage mappings remain after VCPU migration.
Fixes: b79bf2025dbc ("RISC-V: KVM: Rename and move kvm_riscv_local_tlb_sanitize()")
Signed-off-by: Hui Min Mina Chou <minachou@...estech.com>
Signed-off-by: Ben Zong-You Xie <ben717@...estech.com>
---
arch/riscv/kvm/vmid.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c
index 3b426c800480..38c6f532a6f8 100644
--- a/arch/riscv/kvm/vmid.c
+++ b/arch/riscv/kvm/vmid.c
@@ -146,4 +146,10 @@ void kvm_riscv_gstage_vmid_sanitize(struct kvm_vcpu *vcpu)
vmid = READ_ONCE(vcpu->kvm->arch.vmid.vmid);
kvm_riscv_local_hfence_gvma_vmid_all(vmid);
+
+ /*
+ * Flush VS-stage TLBs entry after VCPU migration to avoid using
+ * stale entries.
+ */
+ kvm_riscv_local_hfence_vvma_all(vmid);
}
--
2.34.1
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