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Message-ID: <20251009082013.1331361-4-lzampier@redhat.com>
Date: Thu, 9 Oct 2025 09:20:13 +0100
From: Lucas Zampieri <lzampier@...hat.com>
To: linux-kernel@...r.kernel.org
Cc: devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org,
Charles Mirabile <cmirabil@...hat.com>,
Thomas Gleixner <tglx@...utronix.de>,
Paul Walmsley <paul.walmsley@...ive.com>,
Samuel Holland <samuel.holland@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>,
Zhang Xincheng <zhangxincheng@...rarisc.com>
Subject: [PATCH 3/3] irqchip/plic: add support for UltraRISC DP1000 PLIC
From: Charles Mirabile <cmirabil@...hat.com>
Add a new compatible for the plic found in UltraRISC DP1000 with a quirk to
work around a known hardware bug with IRQ claiming.
When claiming an interrupt on the DP1000 PLIC all other interrupts must be
disabled before the claim register is accessed to prevent incorrect
handling of the interrupt.
When the PLIC_QUIRK_CLAIM_REGISTER is present, during plic_handle_irq
the enable state of all interrupts is saved and then all interrupts
except for the first pending one are disabled before reading the claim
register. The interrupts are then restored before further processing of
the claimed interrupt continues.
This modification matches "ultrarisc,dp1000-plic" and has no impact on
other platforms.
Co-developed-by: Zhang Xincheng <zhangxincheng@...rarisc.com>
Signed-off-by: Zhang Xincheng <zhangxincheng@...rarisc.com>
Signed-off-by: Charles Mirabile <cmirabil@...hat.com>
---
drivers/irqchip/irq-sifive-plic.c | 83 ++++++++++++++++++++++++++++++-
1 file changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 9c4af7d58846..a7b51a925e96 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -49,6 +49,8 @@
#define CONTEXT_ENABLE_BASE 0x2000
#define CONTEXT_ENABLE_SIZE 0x80
+#define PENDING_BASE 0x1000
+
/*
* Each hart context has a set of control registers associated with it. Right
* now there's only two: a source priority threshold over which the hart will
@@ -63,6 +65,7 @@
#define PLIC_ENABLE_THRESHOLD 0
#define PLIC_QUIRK_EDGE_INTERRUPT 0
+#define PLIC_QUIRK_CLAIM_REGISTER 1
struct plic_priv {
struct fwnode_handle *fwnode;
@@ -367,6 +370,82 @@ static const struct irq_domain_ops plic_irqdomain_ops = {
.free = irq_domain_free_irqs_top,
};
+static bool dp1000_isolate_pending_irq(int nr_irq_groups, u32 ie[],
+ void __iomem *pending,
+ void __iomem *enable)
+{
+ u32 pending_irqs = 0;
+ int i, j;
+
+ /* Look for first pending interrupt */
+ for (i = 0; i < nr_irq_groups; i++) {
+ pending_irqs = ie[i] & readl(pending + i * sizeof(u32));
+ if (pending_irqs)
+ break;
+ }
+
+ if (!pending_irqs)
+ return false;
+
+ /* Disable all interrupts but the first pending one */
+ for (j = 0; j < nr_irq_groups; j++) {
+ u32 new_mask = 0;
+
+ if (j == i)
+ /* Extract mask with lowest set bit */
+ new_mask = (pending_irqs & -pending_irqs);
+
+ writel(new_mask, enable + j * sizeof(u32));
+ }
+
+ return true;
+}
+
+static irq_hw_number_t dp1000_get_hwirq(struct plic_handler *handler,
+ void __iomem *claim)
+{
+ void __iomem *enable = handler->enable_base;
+ void __iomem *pending = handler->priv->regs + PENDING_BASE;
+ int nr_irqs = handler->priv->nr_irqs;
+ int nr_irq_groups = DIV_ROUND_UP(nr_irqs, 32);
+ int i;
+ u32 ie[32] = { 0 };
+ irq_hw_number_t hwirq = 0;
+
+ raw_spin_lock(&handler->enable_lock);
+
+ /* Save current interrupt enable state */
+ for (i = 0; i < nr_irq_groups; i++)
+ ie[i] = readl(enable + i * sizeof(u32));
+
+ if (!dp1000_isolate_pending_irq(nr_irq_groups, ie, pending, enable))
+ goto out;
+
+ hwirq = readl(claim);
+
+ /* Restore previous state */
+ for (i = 0; i < nr_irq_groups; i++)
+ writel(ie[i], enable + i * sizeof(u32));
+out:
+ raw_spin_unlock(&handler->enable_lock);
+ return hwirq;
+}
+
+static irq_hw_number_t plic_get_hwirq(struct plic_handler *handler,
+ void __iomem *claim)
+{
+ /*
+ * Due to a hardware bug in the implementation of the claim register
+ * in the UltraRISC DP1000 platform, other interrupts must be disabled
+ * before reading the claim register and restored afterwards.
+ */
+
+ if (test_bit(PLIC_QUIRK_CLAIM_REGISTER, &handler->priv->plic_quirks))
+ return dp1000_get_hwirq(handler, claim);
+
+ return readl(claim);
+}
+
/*
* Handling an interrupt is a two-step process: first you claim the interrupt
* by reading the claim register, then you complete the interrupt by writing
@@ -384,7 +463,7 @@ static void plic_handle_irq(struct irq_desc *desc)
chained_irq_enter(chip, desc);
- while ((hwirq = readl(claim))) {
+ while ((hwirq = plic_get_hwirq(handler, claim))) {
int err = generic_handle_domain_irq(handler->priv->irqdomain,
hwirq);
if (unlikely(err)) {
@@ -432,6 +511,8 @@ static const struct of_device_id plic_match[] = {
.data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
{ .compatible = "thead,c900-plic",
.data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
+ { .compatible = "ultrarisc,dp1000-plic",
+ .data = (const void *)BIT(PLIC_QUIRK_CLAIM_REGISTER) },
{}
};
--
2.51.0
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