linux-kernel - Re: [PATCH v3 1/4] dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3

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Message-ID: <066a9598-ad30-4327-be68-87299bba6fda@kernel.org>
Date: Sat, 11 Oct 2025 02:08:49 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Roy Luo <royluo@...gle.com>, Vinod Koul <vkoul@...nel.org>,
 Kishon Vijay Abraham I <kishon@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
 Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
 Philipp Zabel <p.zabel@...gutronix.de>,
 Peter Griffin <peter.griffin@...aro.org>,
 André Draszik <andre.draszik@...aro.org>,
 Tudor Ambarus <tudor.ambarus@...aro.org>
Cc: Joy Chakraborty <joychakr@...gle.com>, Naveen Kumar <mnkumar@...gle.com>,
 Badhri Jagan Sridharan <badhri@...gle.com>, linux-phy@...ts.infradead.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-usb@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH v3 1/4] dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3

On 10/10/2025 22:16, Roy Luo wrote:
> Document the device tree bindings for the DWC3 USB controller found in
> Google Tensor SoCs, starting with the G5 generation.
> 
> The Tensor G5 silicon represents a complete architectural departure from
> previous generations (like gs101), including entirely new clock/reset
> schemes, top-level wrapper and register interface. Consequently,
> existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating
> this new device tree binding.
> 
> The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features
> Dual-Role Device single port with hibernation support.

You still mix, completely unnecessarily, subsystems. For Greg this is
actually even undesired, but regardless don't do this for any cases
because it just makes everything slower or more difficult to apply.

Really, think how maintainers should deal with your patches.

> 
> Signed-off-by: Roy Luo <royluo@...gle.com>
> ---
>  .../bindings/usb/google,gs5-dwc3.yaml         | 141 ++++++++++++++++++
>  1 file changed, 141 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml
> 
> diff --git a/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml
> new file mode 100644
> index 000000000000..6fadea7f41e8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml
> @@ -0,0 +1,141 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (c) 2025, Google LLC
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/google,gs5-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google Tensor Series (G5+) DWC3 USB SoC Controller
> +
> +maintainers:
> +  - Roy Luo <royluo@...gle.com>
> +
> +description:
> +  Describes the DWC3 USB controller block implemented on Google Tensor SoCs,
> +  starting with the G5 generation. Based on Synopsys DWC3 IP, the controller
> +  features Dual-Role Device single port with hibernation add-on.
> +
> +properties:
> +  compatible:
> +    const: google,gs5-dwc3
> +
> +  reg:
> +    items:
> +      - description: Core DWC3 IP registers.
> +      - description: USB host controller configuration registers.
> +      - description: USB custom interrrupts control registers.
> +
> +  reg-names:
> +    items:
> +      - const: dwc3_core
> +      - const: host_cfg
> +      - const: usbint_cfg
> +
> +  interrupts:
> +    items:
> +      - description: Core DWC3 interrupt.
> +      - description: High speed power management event for remote wakeup from hibernation.
> +      - description: Super speed power management event for remote wakeup from hibernation.

Wrap at 80 (see coding style) or just shorten these.

> +
> +  interrupt-names:
> +    items:
> +      - const: dwc_usb3

So just "core"?

> +      - const: hs_pme
> +      - const: ss_pme
> +
> +  clocks:
> +    items:
> +      - description: Non-sticky module clock.
> +      - description: Sticky module clock.
> +      - description: USB2 PHY APB clock.

This looks wrong. This is not the USB2 phy, so how can it consume APB clock?

> +
> +  clock-names:
> +    items:
> +      - const: non_sticky
> +      - const: sticky
> +      - const: u2phy_apb
> +
> +  resets:
> +    items:
> +      - description: Non-sticky module reset.
> +      - description: Sticky module reset.
> +      - description: USB2 PHY APB reset.

This as well.

> +      - description: DRD bus reset.
> +      - description: Top-level reset.
> +
> +  reset-names:
> +    items:
> +      - const: non_sticky
> +      - const: sticky
> +      - const: u2phy_apb
> +      - const: drd_bus
> +      - const: top


Best regards,
Krzysztof