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Message-ID: <b8e8ab20-d499-4eeb-8a4b-a52d366b3b09@kernel.og>
Date: Mon, 13 Oct 2025 14:11:48 -0500
From: Dinh Nguyen <dinguyen@...nel.og>
To: Khairul Anuar Romli <khairul.anuar.romli@...era.com>,
Dinh Nguyen <dinguyen@...nel.org>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>,
Ang Tien Sung <tiensung.ang@...era.com>
Subject: Re: [PATCH v2 1/1] clk: socfpga: agilex5: add clock driver for
Agilex5
On 10/5/25 22:10, Khairul Anuar Romli wrote:
> Add the new Clock manager driver to support new Agilex5 platform. The new
> driver got rid of the clk_parent_data structures as there are no 'clock-names'
> property in the DT bindings and use parent_names internally. This is based on
> the previous feedback from the maintainer.
>
> Signed-off-by: Ang Tien Sung <tiensung.ang@...era.com>
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@...era.com>
> ---
> Changes in v2:
> - Add clk-agilex5 to Makefile
> - Add Kconfig to include Agilex5 clock manager
> - us of.h instead of of_device and of_address
> - use devm_platform_ioremap_resource to simplify the get resource
> - Fix bound-checking coverage struct clock_data
> - Clean up harmless TODO comment
> ---
> drivers/clk/socfpga/Kconfig | 2 +-
> drivers/clk/socfpga/Makefile | 2 +-
> drivers/clk/socfpga/clk-agilex5.c | 561 +++++++++++++++++++++++++++
> drivers/clk/socfpga/clk-gate-s10.c | 53 +++
> drivers/clk/socfpga/clk-periph-s10.c | 41 ++
> drivers/clk/socfpga/clk-pll-s10.c | 36 ++
> drivers/clk/socfpga/stratix10-clk.h | 43 ++
> 7 files changed, 736 insertions(+), 2 deletions(-)
> create mode 100644 drivers/clk/socfpga/clk-agilex5.c
>
<snip>
> +
> +static int agilex5_clkmgr_init(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct device *dev = &pdev->dev;
> + struct stratix10_clock_data *clk_data;
> + void __iomem *base;
> + int i, num_clks;
> +
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + num_clks = AGILEX5_NUM_CLKS;
> +
> + clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
> + num_clks), GFP_KERNEL);
Please fix these 2 warnings from checkpatch --strict:
WARNING: Prefer a maximum 75 chars per line (possible unwrapped commit
description?)
#7:
Add the new Clock manager driver to support new Agilex5 platform. The
new driver
CHECK: Alignment should match open parenthesis
#565: FILE: drivers/clk/socfpga/clk-agilex5.c:504:
+ clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
+ num_clks), GFP_KERNEL);
total: 0 errors, 2 warnings, 1 checks, 768 lines check
Dinh
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