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Message-ID: <14bc2a85-0f1d-3834-9b9c-32654348603a@oss.qualcomm.com>
Date: Mon, 13 Oct 2025 16:46:38 -0700
From: Wesley Cheng <wesley.cheng@....qualcomm.com>
To: Krzysztof Kozlowski <krzk@...nel.org>, krzk+dt@...nel.org,
conor+dt@...nel.org, konrad.dybcio@....qualcomm.com,
dmitry.baryshkov@....qualcomm.com, kishon@...nel.org, vkoul@...nel.org,
gregkh@...uxfoundation.org, robh@...nel.org
Cc: linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
linux-usb@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 02/10] dt-bindings: phy: qcom,qmp-usb: Add Glymur USB
UNI PHY compatible
On 10/13/2025 4:44 PM, Wesley Cheng wrote:
>
>
> On 10/10/2025 5:04 PM, Krzysztof Kozlowski wrote:
>> On 07/10/2025 00:19, Wesley Cheng wrote:
>>> The Glymur USB subsystem contains a multiport controller, which utilizes
>>> two QMP UNI PHYs. Add the proper compatible string for the Glymur
>>> SoC, and
>>> the required clkref clock name.
>>>
>>> Signed-off-by: Wesley Cheng <wesley.cheng@....qualcomm.com>
>>> ---
>>> .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 35 +++++++++++++++++++
>>> 1 file changed, 35 insertions(+)
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
>>> index a1b55168e050..b0ce803d2b49 100644
>>> ---
>>> a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
>>> +++
>>> b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
>>> @@ -16,6 +16,7 @@ description:
>>> properties:
>>> compatible:
>>> enum:
>>> + - qcom,glymur-qmp-usb3-uni-phy
>>> - qcom,ipq5424-qmp-usb3-phy
>>> - qcom,ipq6018-qmp-usb3-phy
>>> - qcom,ipq8074-qmp-usb3-phy
>>> @@ -62,6 +63,8 @@ properties:
>>> vdda-pll-supply: true
>>> + refgen-supply: true
>>> +
>>> "#clock-cells":
>>> const: 0
>>> @@ -157,6 +160,25 @@ allOf:
>>> compatible:
>>> contains:
>>> enum:
>>> + - qcom,glymur-qmp-usb3-uni-phy
>>> + then:
>>> + properties:
>>> + clocks:
>>
>> Missing minItems.
>>
>
> Hi Krzysztof,
>
> Won't the minItems be inherited by the base definition?
>
Ah...are you saying to define minItems to 5 as well, since we need to
have all 5 clocks handles defined to work?
Thanks
Wesley Cheng
>>> + maxItems: 5
>>> + clock-names:
>>> + items:
>>> + - const: aux
>>> + - const: clkref
>>> + - const: ref
>>
>> What is the difference between these two? Which block INPUTs
>> (important!) they represent?
>>
>
> clkref is the TCSR reference clock switch, and the ref is the actual CXO
> handle.
>
> Thanks
> Wesley Cheng
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