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Message-ID: <fc343072-423f-41db-b7ee-1f1496183363@kernel.org>
Date: Mon, 13 Oct 2025 03:23:23 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: André Draszik <andre.draszik@...aro.org>,
 Sylwester Nawrocki <s.nawrocki@...sung.com>,
 Chanwoo Choi <cw00.choi@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>
Cc: Peter Griffin <peter.griffin@...aro.org>,
 Tudor Ambarus <tudor.ambarus@...aro.org>,
 Will McVicker <willmcvicker@...gle.com>, kernel-team@...roid.com,
 linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: samsung: clk-pll: simplify samsung_pll_lock_wait()

On 01/10/2025 17:13, André Draszik wrote:
>  	/*
> @@ -93,25 +92,15 @@ static int samsung_pll_lock_wait(struct samsung_clk_pll *pll,
>  	 * initialized, another when the timekeeping is suspended. udelay() also
>  	 * cannot be used when the clocksource is not running on arm64, since
>  	 * the current timer is used as cycle counter. So a simple busy loop
> -	 * is used here in that special cases. The limit of iterations has been
> -	 * derived from experimental measurements of various PLLs on multiple
> -	 * Exynos SoC variants. Single register read time was usually in range
> -	 * 0.4...1.5 us, never less than 0.4 us.
> +	 * is used here.
> +	 * The limit of iterations has been derived from experimental
> +	 * measurements of various PLLs on multiple Exynos SoC variants. Single
> +	 * register read time was usually in range 0.4...1.5 us, never less than
> +	 * 0.4 us.
>  	 */
> -	if (pll_early_timeout || timekeeping_suspended) {

Please drop now pll_early_timeout, it is not used anymore.

Best regards,
Krzysztof

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