linux-kernel - Re: [PATCH v2 3/3] irqchip/plic: add support for UltraRISC DP1000 PLIC

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Message-ID: <CAOOg__Cx1x0745LCPh5=EMiDeAVUWy+zzGCqb=BQ-RSFoyZDLQ@mail.gmail.com>
Date: Tue, 14 Oct 2025 15:35:18 +0100
From: Lucas Zampieri <lzampier@...hat.com>
To: Vivian Wang <wangruikang@...as.ac.cn>
Cc: Conor Dooley <conor@...nel.org>, linux-kernel@...r.kernel.org, 
	Charles Mirabile <cmirabil@...hat.com>, Thomas Gleixner <tglx@...utronix.de>, 
	Paul Walmsley <paul.walmsley@...ive.com>, Samuel Holland <samuel.holland@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
	Alexandre Ghiti <alex@...ti.fr>, Vivian Wang <dramforever@...e.com>, linux-riscv@...ts.infradead.org, 
	Zhang Xincheng <zhangxincheng@...rarisc.com>
Subject: Re: [PATCH v2 3/3] irqchip/plic: add support for UltraRISC DP1000 PLIC

Hi Conor and Vivian,

On Tue, Oct 14, 2025 at 10:15 AM Vivian Wang <wangruikang@...as.ac.cn> wrote:
>
> Hi Conor,
>
> On 10/14/25 02:30, Conor Dooley wrote:
> > On Mon, Oct 13, 2025 at 12:15:38PM +0100, Lucas Zampieri wrote:
> >> From: Charles Mirabile <cmirabil@...hat.com>
> >>
> >> Add a new compatible for the plic found in UltraRISC DP1000 with a quirk to
> >> work around a known hardware bug with IRQ claiming.
> >>
> >> When claiming an interrupt on the DP1000 PLIC all other interrupts must be
> >> disabled before the claim register is accessed to prevent incorrect
> >> handling of the interrupt.
> >>
> >> When the PLIC_QUIRK_CLAIM_REGISTER is present, during plic_handle_irq
> >> the enable state of all interrupts is saved and then all interrupts
> >> except for the first pending one are disabled before reading the claim
> >> register. The interrupts are then restored before further processing of
> >> the claimed interrupt continues.
> >>
> >> The driver matches on "ultrarisc,cp100-plic" to apply the quirk to all
> >> SoCs using UR-CP100 cores, regardless of the specific SoC implementation.
> > Why is that? I expect that you're doing that intentionally given the
> > ultrarisc employee listed as a co-developer, but with only one SoC using
> > this IP core it seems possible that this bug in the hardware could be
> > fixed for other SoCs that are built using this IP core.
> > Is there a plan to, for example, change the core version to UR-CP101
> > when the bug is fixed?
>
> I originally proposed to match on ultrarisc,cp100-plic under the
> assumption that it would be the case.
>
As far as I was able to verify with UltraRisc, this is a bug with the
cp100 cores and not the DP-1000 SoC, what that means is that any other
board using those cp100 cores should have the same bug. And I agree
that the function naming in this patch makes it confusing and seem
like this is an issue to the dp1000, I'll reword those in a v3.

> Furthermore, it is my understanding that if the bug is fixed in, say,
> UR-DP1001, then the PLIC node can simply be
>
>     compatible = "ultrarisc,dp1001-plic", "sifive,plic-1.0.0";
>
> I meant my reply that I had assumed this bug was associated with the
> UR-CP100 core, but I should have stated so more clearly.
>
> Vivian "dramforever" Wang
>

Lucas Zampieri