linux-kernel - Re: [PATCH v2 3/3] irqchip/plic: add support for UltraRISC DP1000 PLIC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <6b7c3c90-d3bd-4d75-9cc0-74d3945fbdfd@iscas.ac.cn>
Date: Tue, 14 Oct 2025 17:14:17 +0800
From: Vivian Wang <wangruikang@...as.ac.cn>
To: Conor Dooley <conor@...nel.org>, Lucas Zampieri <lzampier@...hat.com>
Cc: linux-kernel@...r.kernel.org, Charles Mirabile <cmirabil@...hat.com>,
 Thomas Gleixner <tglx@...utronix.de>,
 Paul Walmsley <paul.walmsley@...ive.com>,
 Samuel Holland <samuel.holland@...ive.com>,
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
 Alexandre Ghiti <alex@...ti.fr>, Vivian Wang <dramforever@...e.com>,
 linux-riscv@...ts.infradead.org, Zhang Xincheng <zhangxincheng@...rarisc.com>
Subject: Re: [PATCH v2 3/3] irqchip/plic: add support for UltraRISC DP1000
 PLIC

Hi Conor,

On 10/14/25 02:30, Conor Dooley wrote:
> On Mon, Oct 13, 2025 at 12:15:38PM +0100, Lucas Zampieri wrote:
>> From: Charles Mirabile <cmirabil@...hat.com>
>>
>> Add a new compatible for the plic found in UltraRISC DP1000 with a quirk to
>> work around a known hardware bug with IRQ claiming.
>>
>> When claiming an interrupt on the DP1000 PLIC all other interrupts must be
>> disabled before the claim register is accessed to prevent incorrect
>> handling of the interrupt.
>>
>> When the PLIC_QUIRK_CLAIM_REGISTER is present, during plic_handle_irq
>> the enable state of all interrupts is saved and then all interrupts
>> except for the first pending one are disabled before reading the claim
>> register. The interrupts are then restored before further processing of
>> the claimed interrupt continues.
>>
>> The driver matches on "ultrarisc,cp100-plic" to apply the quirk to all
>> SoCs using UR-CP100 cores, regardless of the specific SoC implementation.
> Why is that? I expect that you're doing that intentionally given the
> ultrarisc employee listed as a co-developer, but with only one SoC using
> this IP core it seems possible that this bug in the hardware could be
> fixed for other SoCs that are built using this IP core.
> Is there a plan to, for example, change the core version to UR-CP101
> when the bug is fixed?

I originally proposed to match on ultrarisc,cp100-plic under the
assumption that it would be the case.

Furthermore, it is my understanding that if the bug is fixed in, say,
UR-DP1001, then the PLIC node can simply be

    compatible = "ultrarisc,dp1001-plic", "sifive,plic-1.0.0";

I meant my reply that I had assumed this bug was associated with the
UR-CP100 core, but I should have stated so more clearly. 

Vivian "dramforever" Wang