linux-kernel - [PATCH] clk: renesas: cpg-mssr: Add read-back and delay handling for RZ/T2H MSTP

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Message-ID: <20251014105348.93705-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Tue, 14 Oct 2025 11:53:48 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>
Cc: linux-renesas-soc@...r.kernel.org,
	linux-clk@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Prabhakar <prabhakar.csengg@...il.com>,
	Biju Das <biju.das.jz@...renesas.com>,
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH] clk: renesas: cpg-mssr: Add read-back and delay handling for RZ/T2H MSTP

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>

On the RZ/T2H SoC, a specific sequence is required when releasing a
module from the module stop state (i.e. when clearing the corresponding
bit in the MSTPCRm register to '0'). After writing to the MSTPCRm
register, a read-back of the same register must be performed, followed
by at least seven dummy reads of any register within the IP block that
is being released.

To avoid mapping device registers for this purpose, a short delay is
introduced after the read-back to ensure proper hardware stabilization
before the module becomes accessible.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
Hi Geert,

I made use of the timed_read_poll_timeout_atomic() macro to print the
delay after the read operation. With first case I printed the value read
from the register and in the second case I just printed the number of
loops and time taken. So to be on the safe side I have added a udelay(10)
after the read operation. Please find below the output from both the cases.

#1 With value printed
[    1.468936] read_7times_init: poll OK after 0 loops 223 ticks, 10000 ns left of 10 us
[    1.477719] read_7times: read 0: ff002104
[    1.482358] read_7times_init: poll OK after 0 loops 126 ticks, 10000 ns left of 10 us
[    1.491331] read_7times: read 1: ff002104
[    1.495901] read_7times_init: poll OK after 0 loops 100 ticks, 10000 ns left of 10 us
[    1.504692] read_7times: read 2: ff002104
[    1.509261] read_7times_init: poll OK after 0 loops 103 ticks, 10000 ns left of 10 us
[    1.518052] read_7times: read 3: ff002104
[    1.522692] read_7times_init: poll OK after 0 loops 100 ticks, 10000 ns left of 10 us
[    1.531665] read_7times: read 4: ff002104
[    1.536209] read_7times_init: poll OK after 0 loops 102 ticks, 10000 ns left of 10 us
[    1.545183] read_7times: read 5: ff002104
[    1.549726] read_7times_init: poll OK after 0 loops 84 ticks, 10000 ns left of 10 us
[    1.558456] read_7times: read 6: ff002104

#2 Without values being printed
[    1.469581] read_7times_init: poll OK after 0 loops 255 ticks, 10000 ns left of 10 us
[    1.478668] read_7times_init: poll OK after 0 loops 130 ticks, 10000 ns left of 10 us
[    1.487650] read_7times_init: poll OK after 0 loops 101 ticks, 10000 ns left of 10 us
[    1.496527] read_7times_init: poll OK after 0 loops 99 ticks, 10000 ns left of 10 us
[    1.505231] read_7times_init: poll OK after 0 loops 96 ticks, 10000 ns left of 10 us
[    1.514109] read_7times_init: poll OK after 0 loops 97 ticks, 10000 ns left of 10 us
[    1.522883] read_7times_init: poll OK after 0 loops 99 ticks, 10000 ns left of 10 us

Cheers, Prabhakar
---
 drivers/clk/renesas/renesas-cpg-mssr.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index c9598fd1f8cd..4e9c1bcaf968 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -308,10 +308,21 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
 
 	spin_unlock_irqrestore(&priv->pub.rmw_lock, flags);
 
-	if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A ||
-	    priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
+	if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
 		return 0;
 
+	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
+		/*
+		 * For the RZ/T2H case, it is necessary to perform a read-back after
+		 * accessing the MSTPCRm register and to dummy-read any register of
+		 * the IP at least seven times. Instead of memory-mapping the IP
+		 * register, we simply add a delay after the read operation.
+		 */
+		cpg_rzt2h_mstp_read(hw, priv->control_regs[reg]);
+		udelay(10);
+		return 0;
+	}
+
 	error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg],
 					  value, !(value & bitmask), 0, 10);
 	if (error)
-- 
2.43.0