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Message-ID: <CAMuHMdVzuRhD-r=gSzm2FDDsAOr+Xu1fWyN7ky-U0NoJWXY=qw@mail.gmail.com>
Date: Tue, 21 Oct 2025 15:28:37 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH] clk: renesas: cpg-mssr: Add read-back and delay handling
for RZ/T2H MSTP
On Tue, 14 Oct 2025 at 12:54, Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> On the RZ/T2H SoC, a specific sequence is required when releasing a
> module from the module stop state (i.e. when clearing the corresponding
> bit in the MSTPCRm register to '0'). After writing to the MSTPCRm
> register, a read-back of the same register must be performed, followed
> by at least seven dummy reads of any register within the IP block that
> is being released.
>
> To avoid mapping device registers for this purpose, a short delay is
> introduced after the read-back to ensure proper hardware stabilization
> before the module becomes accessible.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in renesas-clk for v6.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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