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Message-ID: <409ad505-8846-443e-8d71-baca3c9aef21@sirena.org.uk>
Date: Wed, 15 Oct 2025 13:01:23 +0100
From: Mark Brown <broonie@...nel.org>
To: Nuno Sá <noname.nuno@...il.com>
Cc: David Lechner <dlechner@...libre.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Marcelo Schmitt <marcelo.schmitt@...log.com>,
Michael Hennerich <michael.hennerich@...log.com>,
Nuno Sá <nuno.sa@...log.com>,
Jonathan Cameron <jic23@...nel.org>,
Andy Shevchenko <andy@...nel.org>,
Sean Anderson <sean.anderson@...ux.dev>, linux-spi@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-iio@...r.kernel.org
Subject: Re: [PATCH 3/6] spi: add multi_bus_mode field to struct spi_transfer
On Wed, Oct 15, 2025 at 11:16:01AM +0100, Nuno Sá wrote:
> On Tue, 2025-10-14 at 17:02 -0500, David Lechner wrote:
> > controller < data bits < peripheral
> > ---------- ---------------- ----------
> > SDI 0 0-0-0-1-0-0-0-1 SDO 0
> > SDI 1 1-0-0-0-1-0-0-0 SDO 1
> Out of curiosity, how does this work for devices like AD4030 where the same word
> is kind of interleaved between SDO lines? I guess it works the same (in terms of
> SW) and is up to some IP core (typically in the FPGA) to "re-assemble" the word?
So combined with the existing parallel SPI support?
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