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Message-ID: <CACRpkdaOuih=CVuGVgpfwP921g5KSd1Dm5v8oyyYq0pJdrzgHw@mail.gmail.com>
Date: Fri, 17 Oct 2025 00:51:06 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Gary Yang <gary.yang@...tech.com>
Cc: "robh@...nel.org" <robh@...nel.org>, "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
"conor+dt@...nel.org" <conor+dt@...nel.org>,
"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>,
cix-kernel-upstream <cix-kernel-upstream@...tech.com>
Subject: Re: [PATCH v3 2/3] pinctrl: cix: Add pin-controller support for sky1
On Thu, Oct 16, 2025 at 7:41 AM Gary Yang <gary.yang@...tech.com> wrote:
> GPIO IP on Sky1 is Cadence, not Synopsys designware. We wants to do
> it when upstream GPIO driver in the future.
> Are you agree?
Yes no problem. (I misremembered that it was Cadence, not Synopsys...)
When I look at the Cadence driver I see it needs some modifications
if it should work properly with GPIO ranges and interoperate with
pin controllers. It needs to call gpiochip_generic_request() and
gpiochip_generic_free() from its request/free functions, and
preferably also gpiochip_generic_config() which will extend
the gpiolib to call down to the pin controller and take control
over line properties.
But let's do that in a separate patch!
Yours,
Linus Walleij
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