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Message-ID: <20251016131327.19141-2-ovidiu.panait.rb@renesas.com>
Date: Thu, 16 Oct 2025 13:13:25 +0000
From: Ovidiu Panait <ovidiu.panait.rb@...esas.com>
To: john.madieu.xa@...renesas.com,
	rafael@...nel.org,
	daniel.lezcano@...aro.org,
	rui.zhang@...el.com,
	lukasz.luba@....com,
	robh@...nel.org,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	geert+renesas@...der.be,
	magnus.damm@...il.com,
	mturquette@...libre.com,
	sboyd@...nel.org
Cc: linux-pm@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-renesas-soc@...r.kernel.org,
	linux-clk@...r.kernel.org
Subject: [PATCH 1/3] clk: renesas: r9a09g057: Add clock and reset entries for TSU

Add module clock and reset entries for the TSU0 and TSU1 blocks on the
Renesas RZ/V2H (R9A09G057) SoC.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@...esas.com>
---
 drivers/clk/renesas/r9a09g057-cpg.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index 4e47fea3f894..e865a70a7f25 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -379,6 +379,10 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
 						BUS_MSTOP(3, BIT(4))),
 	DEF_MOD("gpu_0_ace_clk",		CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
 						BUS_MSTOP(3, BIT(4))),
+	DEF_MOD("tsu_0_pclk",			CLK_QEXTAL, 16, 9, 8, 9,
+						BUS_MSTOP(5, BIT(2))),
+	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,
+						BUS_MSTOP(2, BIT(15))),
 };
 
 static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
@@ -449,6 +453,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
 	DEF_RST(13, 13, 6, 14),		/* GPU_0_RESETN */
 	DEF_RST(13, 14, 6, 15),		/* GPU_0_AXI_RESETN */
 	DEF_RST(13, 15, 6, 16),		/* GPU_0_ACE_RESETN */
+	DEF_RST(15, 7, 7, 8),		/* TSU_0_PRESETN */
+	DEF_RST(15, 8, 7, 9),		/* TSU_1_PRESETN */
 };
 
 const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
-- 
2.51.0


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