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Message-ID: <20251016131327.19141-4-ovidiu.panait.rb@renesas.com>
Date: Thu, 16 Oct 2025 13:13:27 +0000
From: Ovidiu Panait <ovidiu.panait.rb@...esas.com>
To: john.madieu.xa@...renesas.com,
rafael@...nel.org,
daniel.lezcano@...aro.org,
rui.zhang@...el.com,
lukasz.luba@....com,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
geert+renesas@...der.be,
magnus.damm@...il.com,
mturquette@...libre.com,
sboyd@...nel.org
Cc: linux-pm@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: [PATCH 3/3] arm64: dts: renesas: r9a09g057: Add TSU nodes
The Renesas RZ/V2H SoC includes a Thermal Sensor Unit (TSU) block designed
to measure the junction temperature. The device provides real-time
temperature measurements for thermal management, utilizing two dedicated
channels for temperature sensing:
- TSU0, which is located near the DRP-AI block
- TSU1, which is located near the CPU and DRP-AI block
Since TSU1 is physically closer the CPU and the highest temperature
spot, it is used for CPU throttling through a passive trip and cooling
map. TSU0 is configured only with a critical trip.
Add TSU nodes along with thermal zones and keep them enabled in the SoC
DTSI.
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@...esas.com>
---
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 75 ++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index e426b9978e22..e88cfc965415 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -65,6 +65,7 @@ cpu0: cpu@0 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@@ -75,6 +76,7 @@ cpu1: cpu@100 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>;
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@@ -85,6 +87,7 @@ cpu2: cpu@200 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>;
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@@ -95,6 +98,7 @@ cpu3: cpu@300 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>;
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@@ -285,6 +289,32 @@ sys: system-controller@...30000 {
resets = <&cpg 0x30>;
};
+ tsu0: thermal@...00000 {
+ compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu";
+ reg = <0 0x11000000 0 0x1000>;
+ interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "adi", "adcmpi";
+ clocks = <&cpg CPG_MOD 0x109>;
+ resets = <&cpg 0xf7>;
+ power-domains = <&cpg>;
+ #thermal-sensor-cells = <0>;
+ renesas,tsu-trim = <&sys 0x320>;
+ };
+
+ tsu1: thermal@...02000 {
+ compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu";
+ reg = <0 0x14002000 0 0x1000>;
+ interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "adi", "adcmpi";
+ clocks = <&cpg CPG_MOD 0x10a>;
+ resets = <&cpg 0xf8>;
+ power-domains = <&cpg>;
+ #thermal-sensor-cells = <0>;
+ renesas,tsu-trim = <&sys 0x330>;
+ };
+
xspi: spi@...30000 {
compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi";
reg = <0 0x11030000 0 0x10000>,
@@ -1326,6 +1356,51 @@ stmmac_axi_setup: stmmac-axi-config {
snps,blen = <16 8 4 0 0 0 0>;
};
+ thermal-zones {
+ sensor1_thermal: sensor1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&tsu0>;
+
+ trips {
+ sensor1_crit: sensor1-crit {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ sensor2_thermal: sensor2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&tsu1>;
+
+ cooling-maps {
+ map0 {
+ trip = <&sensor2_target>;
+ cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
+ <&cpu2 0 3>, <&cpu3 0 3>;
+ contribution = <1024>;
+ };
+ };
+
+ trips {
+ sensor2_target: trip-point {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ sensor2_crit: sensor2-crit {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
--
2.51.0
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