linux-kernel - Re: [PATCH v2] x86/mce: Add support for PHYSADDRV and PHYSADDRVALIDSUPPORTED bits

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Message-ID: <020798df-1abf-4097-a8b7-ecf13b7eec9a@amd.com>
Date: Fri, 17 Oct 2025 11:44:24 -0500
From: "Naik, Avadhut" <avadnaik@....com>
To: Yazen Ghannam <yazen.ghannam@....com>, bp@...en8.de
Cc: x86@...nel.org, linux-edac@...r.kernel.org, tony.luck@...el.com,
 linux-kernel@...r.kernel.org, Avadhut Naik <avadhut.naik@....com>
Subject: Re: [PATCH v2] x86/mce: Add support for PHYSADDRV and
 PHYSADDRVALIDSUPPORTED bits



On 10/17/2025 09:31, Yazen Ghannam wrote:
> On Wed, Oct 15, 2025 at 05:22:25PM +0000, Avadhut Naik wrote:
>> Starting with Zen6, AMD's Scalable MCA systems will incorporate two new
>> bits in MCA_STATUS and MCA_CONFIG MSRs. These bits will indicate if a
>> valid System Physical Address (SPA) is present in MCA_ADDR.
>>
>> PhysAddrValidSupported bit (MCA_CONFIG[11]) serves as the architectural
>> indicator and states if PhysAddrV bit (MCA_STATUS[54]) is Reserved or
>> if it indicates validity of SPA in MCA_ADDR.
>>
>> PhysAddrV bit (MCA_STATUS[54]) advertises if MCA_ADDR contains valid
>> SPA or if it is implementation specific.
>>
>> Use and prefer MCA_STATUS[PhysAddrV] when checking for a usable address.
>>
>> Signed-off-by: Avadhut Naik <avadhut.naik@....com>
>> ---
> 
> Minor nit:
> The $SUBJECT could be simpler, like "Use new physical address valid
> bit". And leave the details and proper field names for the commit
> message.
> 
> But in any case, looks good to me.
> 
> Reviewed-by: Yazen Ghannam <yazen.ghannam@....com>
> 
Thanks Yazen!

Hi Boris,

If you don't have any further feedback on this, do you want me to send
another version with the subject changed per Yazen's recommendation?
Or would you take care of it at your end?

> Thanks,
> Yazen

-- 
Thanks,
Avadhut Naik