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Message-ID: <aPaJ479zH/90fJ2d@lizhi-Precision-Tower-5810>
Date: Mon, 20 Oct 2025 15:13:39 -0400
From: Frank Li <Frank.li@....com>
To: Alex Elder <elder@...cstar.com>
Cc: han.xu@....com, broonie@...nel.org, dlan@...too.org,
	guodong@...cstar.com, linux-spi@...r.kernel.org,
	imx@...ts.linux.dev, spacemit@...ts.linux.dev,
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 4/8] spi: fsl-qspi: add a clock disable quirk

On Mon, Oct 20, 2025 at 11:51:47AM -0500, Alex Elder wrote:
> The SpacemiT K1 SoC QSPI implementation needs to avoid shutting
> off the clock when changing its rate.  Add a new quirk to indicate
> the clock should not be disabled/enabled when changing its rate
> for operations.
>
> Signed-off-by: Alex Elder <elder@...cstar.com>
> ---
>  drivers/spi/spi-fsl-qspi.c | 21 +++++++++++++++++----
>  1 file changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
> index 1e27647dd2a09..703a7df394c00 100644
> --- a/drivers/spi/spi-fsl-qspi.c
> +++ b/drivers/spi/spi-fsl-qspi.c
> @@ -197,6 +197,11 @@
>   */
>  #define QUADSPI_QUIRK_USE_TDH_SETTING	BIT(5)
>
> +/*
> + * Do not disable the "qspi" clock when changing its rate.
> + */
> +#define QUADSPI_QUIRK_NO_CLK_DISABLE	BIT(6)

NO_CLK_DISALBE look likes not clk disable capability. Maybe

QUADSPI_QUIRK_SKIP_CLK_DISABLE

> +
>  struct fsl_qspi_devtype_data {
>  	unsigned int rxfifo;
>  	unsigned int txfifo;
> @@ -306,6 +311,11 @@ static inline int needs_tdh_setting(struct fsl_qspi *q)
>  	return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
>  }
>
> +static inline int needs_clk_disable(struct fsl_qspi *q)

bool type?

Frank

> +{
> +	return !(q->devtype_data->quirks & QUADSPI_QUIRK_NO_CLK_DISABLE);
> +}
> +
>  /*
>   * An IC bug makes it necessary to rearrange the 32-bit data.
>   * Later chips, such as IMX6SLX, have fixed this bug.
> @@ -536,15 +546,18 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi,
>  	if (needs_4x_clock(q))
>  		rate *= 4;
>
> -	fsl_qspi_clk_disable_unprep(q);
> +	if (needs_clk_disable(q))
> +		fsl_qspi_clk_disable_unprep(q);
>
>  	ret = clk_set_rate(q->clk, rate);
>  	if (ret)
>  		return;
>
> -	ret = fsl_qspi_clk_prep_enable(q);
> -	if (ret)
> -		return;
> +	if (needs_clk_disable(q)) {
> +		ret = fsl_qspi_clk_prep_enable(q);
> +		if (ret)
> +			return;
> +	}
>
>  	q->selected = spi_get_chipselect(spi, 0);
>
> --
> 2.48.1
>

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