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Message-ID: <20251020074211.8942-13-xiandong.wang@mediatek.com>
Date: Mon, 20 Oct 2025 15:40:25 +0800
From: Xiandong Wang <xiandong.wang@...iatek.com>
To: Jassi Brar <jassisinghbrar@...il.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, Yongqiang Niu
<yongqiang.niu@...iatek.com>
CC: <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>,
<sirius.wang@...iatek.com>, <vince-wl.liu@...iatek.com>,
<jh.hsu@...iatek.com>, <Project_Global_Chrome_Upstream_Group@...iatek.com>,
Xiandong Wang <xiandong.wang@...iatek.com>
Subject: [PATCH v1 12/13] drm/mediatek: Add support for mt8189 mmsys driver probe
mmsys probe for mt8189
Signed-off-by: Xiandong Wang <xiandong.wang@...iatek.com>
---
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 2 ++
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 40 ++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_disp_ovl.h | 2 ++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 8 +++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 39 +++++++++++++++++++++++
5 files changed, 91 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index ac6620e10262..b83ecd5404c6 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -498,6 +498,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
[DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
[DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
+ [DDP_COMPONENT_COMP0_OUT_CB4] = { MTK_DISP_VIRTUAL, -1, NULL },
+ [DDP_COMPONENT_COMP0_OUT_CB5] = { MTK_DISP_VIRTUAL, -1, NULL },
};
static bool mtk_ddp_comp_find(struct device *dev,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 7cd3978beb98..f1fa1f1c3ff0 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -110,6 +110,32 @@ const u32 mt8173_ovl_formats[] = {
const size_t mt8173_ovl_formats_len = ARRAY_SIZE(mt8173_ovl_formats);
+const u32 mt8189_ovl_formats[] = {
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_BGRX1010102,
+ DRM_FORMAT_BGRA1010102,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_RGBX1010102,
+ DRM_FORMAT_RGBA1010102,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+};
+
+const size_t mt8189_ovl_formats_len = ARRAY_SIZE(mt8189_ovl_formats);
+
const u32 mt8195_ovl_formats[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_ARGB8888,
@@ -779,6 +805,18 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
.num_formats = mt8173_ovl_formats_len,
};
+static const struct mtk_disp_ovl_data mt8189_ovl_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 4,
+ .fmt_rgb565_is_0 = true,
+ .smi_id_en = true,
+ .supports_afbc = true,
+ .formats = mt8189_formats,
+ .num_formats = ARRAY_SIZE(mt8189_formats),
+ .supports_clrfmt_ext = true,
+};
+
static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
.addr = DISP_REG_OVL_ADDR_MT8173,
.gmc_bits = 10,
@@ -823,6 +861,8 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
.data = &mt8183_ovl_driver_data},
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
.data = &mt8183_ovl_2l_driver_data},
+ { .compatible = "mediatek,mt8189-disp-ovl",
+ .data = &mt8189_ovl_driver_data},
{ .compatible = "mediatek,mt8192-disp-ovl",
.data = &mt8192_ovl_driver_data},
{ .compatible = "mediatek,mt8192-disp-ovl-2l",
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
index 431567538eb5..675254e786d4 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
@@ -16,6 +16,8 @@
extern const u32 mt8173_ovl_formats[];
extern const size_t mt8173_ovl_formats_len;
+extern const u32 mt8189_ovl_formats[];
+extern const size_t mt8189_ovl_formats_len;
extern const u32 mt8195_ovl_formats[];
extern const size_t mt8195_ovl_formats_len;
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index c9d41d75e7f2..593d9d144218 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -394,6 +394,12 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
.num_formats = ARRAY_SIZE(mt8173_formats),
};
+static const struct mtk_disp_rdma_data mt8189_rdma_driver_data = {
+ .fifo_size = 1920,
+ .formats = mt8173_formats,
+ .num_formats = ARRAY_SIZE(mt8173_formats),
+};
+
static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
.fifo_size = 1920,
.formats = mt8173_formats,
@@ -407,6 +413,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
.data = &mt8173_rdma_driver_data},
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = &mt8183_rdma_driver_data},
+ { .compatible = "mediatek,mt8189-disp-rdma",
+ .data = &mt8189_rdma_driver_data},
{ .compatible = "mediatek,mt8195-disp-rdma",
.data = &mt8195_rdma_driver_data},
{},
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 4c19cffafd0f..9e6d949e5d17 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -187,11 +187,27 @@ static const unsigned int mt8188_mtk_ddp_main[] = {
DDP_COMPONENT_DITHER0,
};
+static const unsigned int mt8189_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COMP0_OUT_CB4,
+};
+
+static const unsigned int mt8189_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_RDMA1,
+ DDP_COMPONENT_COMP0_OUT_CB5,
+};
+
static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = {
{0, DDP_COMPONENT_DP_INTF0},
{0, DDP_COMPONENT_DSI0},
};
+static const struct mtk_drm_route mt8189_mtk_ddp_ext_routes[] = {
+ {1, DDP_COMPONENT_DSI0},
+};
+
static const struct mtk_drm_route mt8196_mtk_ddp_routes[] = {
{2, DDP_COMPONENT_DSI0},
};
@@ -347,6 +363,19 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
.min_height = 1,
};
+static const struct mtk_mmsys_driver_data mt8189_mmsys_driver_data = {
+ .main_path = mt8189_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8189_mtk_ddp_main),
+ .mmsys_dev_num = 1,
+ .ext_path = mt8189_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8189_mtk_ddp_ext),
+ .conn_routes = mt8189_mtk_ddp_ext_routes,
+ .num_conn_routes = ARRAY_SIZE(mt8189_mtk_ddp_ext_routes),
+ .max_width = 8191,
+ .min_width = 1,
+ .min_height = 1,
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.main_path = mt8192_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
@@ -454,6 +483,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8188_vdosys0_driver_data},
{ .compatible = "mediatek,mt8188-vdosys1",
.data = &mt8195_vdosys1_driver_data},
+ { .compatible = "mediatek,mt8189-mmsys",
+ .data = &mt8189_mmsys_driver_data},
{ .compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data},
{ .compatible = "mediatek,mt8195-mmsys",
@@ -883,6 +914,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8188-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8189-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX},
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8195-disp-mutex",
@@ -899,6 +932,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8183-disp-ovl",
.data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8189-disp-ovl",
+ .data = (void *)MTK_DISP_OVL},
{ .compatible = "mediatek,mt8192-disp-ovl",
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8195-disp-ovl",
@@ -923,6 +958,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8189-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8195-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-ufoe",
@@ -957,6 +994,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8188-dsi",
.data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8189-dsi",
+ .data = (void *)MTK_DSI },
{ }
};
--
2.46.0
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