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Message-ID: <20251020074211.8942-12-xiandong.wang@mediatek.com>
Date: Mon, 20 Oct 2025 15:40:24 +0800
From: Xiandong Wang <xiandong.wang@...iatek.com>
To: Jassi Brar <jassisinghbrar@...il.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, Yongqiang Niu
<yongqiang.niu@...iatek.com>
CC: <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>,
<sirius.wang@...iatek.com>, <vince-wl.liu@...iatek.com>,
<jh.hsu@...iatek.com>, <Project_Global_Chrome_Upstream_Group@...iatek.com>,
Xiandong Wang <xiandong.wang@...iatek.com>
Subject: [PATCH v1 11/13] soc: mediatek: add mmsys support for MT8189
Add driver data for MT8189 and add the routing table for each mmsys.
Signed-off-by: Xiandong Wang <xiandong.wang@...iatek.com>
---
drivers/soc/mediatek/mt8189-mmsys.h | 300 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 12 +
include/linux/soc/mediatek/mtk-mmsys.h | 5 +
3 files changed, 317 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8189-mmsys.h
diff --git a/drivers/soc/mediatek/mt8189-mmsys.h b/drivers/soc/mediatek/mt8189-mmsys.h
new file mode 100644
index 000000000000..31378b6ee100
--- /dev/null
+++ b/drivers/soc/mediatek/mt8189-mmsys.h
@@ -0,0 +1,300 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 MediaTek Inc.
+ */
+
+#ifndef __SOC_MEDIATEK_MT8189_MMSYS_H
+#define __SOC_MEDIATEK_MT8189_MMSYS_H
+
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define MT8189_MMSYS_SW0_RST_B 0x190
+
+#define MT8189_MMSYS_GCE_EVENT_SEL 0x308
+#define MT8189_EVENT_GCE_EN (BIT(0) | BIT(1))
+
+#define MT8189_DISP_OVL0_OUT0_MOUT_EN 0xc10
+ #define MT8189_MOUT_DISP_OVL0_TO_DISP_RSZ0 BIT(0)
+ #define MT8189_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(1)
+ #define MT8189_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(2)
+
+#define MT8189_DISP_OVL1_OUT0_MOUT_EN 0xc14
+ #define MT8189_MOUT_DISP_OVL1_TO_DISP_RSZ1 BIT(0)
+ #define MT8189_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(1)
+ #define MT8189_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(2)
+#define MT8189_DISP_OVL_OUT0_MOUT_MASK 0x7
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR0_MOUT_EN 0xc74
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_DISP_DSC_WRAP0_0 BIT(0)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_DISP_DSC_WRAP0_1 BIT(1)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_VPP_MERGE0_0 BIT(2)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_VPP_MERGE0_1 BIT(3)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_COMP_OUT_CROSSBAR4 BIT(4)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_COMP_OUT_CROSSBAR5 BIT(5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR1_MOUT_EN 0xc78
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_DISP_DSC_WRAP0_0 BIT(0)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_DISP_DSC_WRAP0_1 BIT(1)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_VPP_MERGE0_0 BIT(2)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_VPP_MERGE0_1 BIT(3)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_COMP_OUT_CROSSBAR4 BIT(4)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_COMP_OUT_CROSSBAR5 BIT(5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR2_MOUT_EN 0xc7c
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_DISP_DSC_WRAP0_0 BIT(0)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_DISP_DSC_WRAP0_1 BIT(1)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_VPP_MERGE0_0 BIT(2)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_VPP_MERGE0_1 BIT(3)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_COMP_OUT_CROSSBAR4 BIT(4)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_COMP_OUT_CROSSBAR5 BIT(5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR3_MOUT_EN 0xc80
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_DISP_DSC_WRAP0_0 BIT(0)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_DISP_DSC_WRAP0_1 BIT(1)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_VPP_MERGE0_0 BIT(2)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_VPP_MERGE0_1 BIT(3)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_COMP_OUT_CROSSBAR4 BIT(4)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_COMP_OUT_CROSSBAR5 BIT(5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR4_MOUT_EN 0xc84
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_DISP_DSC_WRAP0_0 BIT(0)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_DISP_DSC_WRAP0_1 BIT(1)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_VPP_MERGE0_0 BIT(2)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_VPP_MERGE0_1 BIT(3)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_COMP_OUT_CROSSBAR4 BIT(4)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_COMP_OUT_CROSSBAR5 BIT(5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR5_MOUT_EN 0xc88
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_DISP_DSC_WRAP0_0 BIT(0)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_DISP_DSC_WRAP0_1 BIT(1)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_VPP_MERGE0_0 BIT(2)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_VPP_MERGE0_1 BIT(3)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_COMP_OUT_CROSSBAR4 BIT(4)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_COMP_OUT_CROSSBAR5 BIT(5)
+#define MT8189_OVL_PQ_OUT_CROSSBAR_MOUT_MASK 0x3f
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR0_SEL_IN 0xc8c
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_DITER0 (0)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_RDMA0_RSZ0_SOUT (1)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_OVL0_OUT0_MOUT (2)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_DITER1 (3)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_RDMA1_RSZ1_SOUT (4)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_OVL1_OUT0_MOUT (5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR1_SEL_IN 0xc90
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_DITER0 (0)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_RDMA0_RSZ0_SOUT (1)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_OVL0_OUT0_MOUT (2)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_DITER1 (3)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_RDMA1_RSZ1_SOUT (4)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_OVL1_OUT0_MOUT (5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR2_SEL_IN 0xc94
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_DITER0 (0)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_RDMA0_RSZ0_SOUT (1)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_OVL0_OUT0_MOUT (2)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_DITER1 (3)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_RDMA1_RSZ1_SOUT (4)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_OVL1_OUT0_MOUT (5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR3_SEL_IN 0xc98
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_DITER0 (0)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_RDMA0_RSZ0_SOUT (1)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_FROM_DISP_OVL0_OUT0_MOUT (2)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_DITER1 (3)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_RDMA1_RSZ1_SOUT (4)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_OVL1_OUT0_MOUT (5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR4_SEL_IN 0xc9c
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_DITER0 (0)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_RDMA0_RSZ0_SOUT (1)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_OVL0_OUT0_MOUT (2)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_DITER1 (3)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_RDMA1_RSZ1_SOUT (4)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_OVL1_OUT0_MOUT (5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR5_SEL_IN 0xca0
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_DITER0 (0)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_RDMA0_RSZ0_SOUT (1)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_OVL0_OUT0_MOUT (2)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_DITER1 (3)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_RDMA1_RSZ1_SOUT (4)
+ #define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_OVL1_OUT0_MOUT (5)
+
+#define MT8189_COMP_OUT_CROSSBAR0_MOUT_EN 0xd70
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_DSI0 BIT(0)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_DVO0 BIT(1)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_DVO1 BIT(2)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DPI0 BIT(3)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_WDMA0 BIT(4)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_WDMA1 BIT(5)
+
+#define MT8189_COMP_OUT_CROSSBAR1_MOUT_EN 0xd74
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_DSI0 BIT(0)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_DVO0 BIT(1)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_DVO1 BIT(2)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DPI0 BIT(3)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_WDMA0 BIT(4)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_WDMA1 BIT(5)
+
+#define MT8189_COMP_OUT_CROSSBAR2_MOUT_EN 0xd78
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_DSI0 BIT(0)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_DVO0 BIT(1)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_DVO1 BIT(2)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DPI0 BIT(3)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_WDMA0 BIT(4)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_WDMA1 BIT(5)
+
+#define MT8189_COMP_OUT_CROSSBAR3_MOUT_EN 0xd7c
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_DSI0 BIT(0)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_DVO0 BIT(1)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_DVO1 BIT(2)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DPI0 BIT(3)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_WDMA0 BIT(4)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_WDMA1 BIT(5)
+
+#define MT8189_COMP_OUT_CROSSBAR4_MOUT_EN 0xd80
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_DSI0 BIT(0)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_DVO0 BIT(1)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_DVO1 BIT(2)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DPI0 BIT(3)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_WDMA0 BIT(4)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_WDMA1 BIT(5)
+
+#define MT8189_COMP_OUT_CROSSBAR5_MOUT_EN 0xd84
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DSI0 BIT(0)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DVO0 BIT(1)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DVO1 BIT(2)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DPI0 BIT(3)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_WDMA0 BIT(4)
+ #define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_WDMA1 BIT(5)
+
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_DISP_DSC_WRAP0_0 BIT(0)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_DISP_DSC_WRAP0_1 BIT(1)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_VPP_MERGE0_0 BIT(2)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_VPP_MERGE0_1 BIT(3)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_COMP_OUT_CROSSBAR4 BIT(4)
+ #define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_COMP_OUT_CROSSBAR5 BIT(5)
+#define MT8189_COMP_OUT_CROSSBAR_MOUT_MASK 0x3f
+
+#define MT8189_COMP_OUT_CROSSBAR0_SEL_IN 0xd88
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_DISP_DSC_WRAP0_0 (0)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_DISP_DSC_WRAP0_1 (1)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_VPP_MERGE0_0 (2)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_VPP_MERGE0_1 (3)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_OVL_PQ_OUT_CROSSBAR4 (4)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_OVL_PQ_OUT_CROSSBAR5 (5)
+
+#define MT8189_COMP_OUT_CROSSBAR1_SEL_IN 0xd8c
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_DISP_DSC_WRAP0_0 (0)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_DISP_DSC_WRAP0_1 (1)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_VPP_MERGE0_0 (2)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_VPP_MERGE0_1 (3)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_OVL_PQ_OUT_CROSSBAR4 (4)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_OVL_PQ_OUT_CROSSBAR5 (5)
+
+#define MT8189_COMP_OUT_CROSSBAR2_SEL_IN 0xd90
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_DISP_DSC_WRAP0_0 (0)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_DISP_DSC_WRAP0_1 (1)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_VPP_MERGE0_0 (2)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_VPP_MERGE0_1 (3)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_OVL_PQ_OUT_CROSSBAR4 (4)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_OVL_PQ_OUT_CROSSBAR5 (5)
+
+#define MT8189_COMP_OUT_CROSSBAR3_SEL_IN 0xd94
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_DISP_DSC_WRAP0_0 (0)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_DISP_DSC_WRAP0_1 (1)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_VPP_MERGE0_0 (2)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_VPP_MERGE0_1 (3)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_OVL_PQ_OUT_CROSSBAR4 (4)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_OVL_PQ_OUT_CROSSBAR5 (5)
+
+#define MT8189_COMP_OUT_CROSSBAR4_SEL_IN 0xd98
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_DISP_DSC_WRAP0_0 (0)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_DISP_DSC_WRAP0_1 (1)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_VPP_MERGE0_0 (2)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_VPP_MERGE0_1 (3)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_OVL_PQ_OUT_CROSSBAR4 (4)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_OVL_PQ_OUT_CROSSBAR5 (5)
+
+#define MT8189_COMP_OUT_CROSSBAR5_SEL_IN 0xd9c
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_DISP_DSC_WRAP0_0 (0)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_DISP_DSC_WRAP0_1 (1)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_VPP_MERGE0_0 (2)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_VPP_MERGE0_1 (3)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_OVL_PQ_OUT_CROSSBAR4 (4)
+ #define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_OVL_PQ_OUT_CROSSBAR5 (5)
+
+#define MT8189_DISP_RDMA0_RSZ0_SOUT_SEL 0xe00
+ #define MT8189_SOUT_DISP_RDMA0_RSZ0_TO_OVL_PQ_OUT_CROSSBAR1 (0)
+ #define MT8189_SOUT_DISP_RDMA0_RSZ0_TO_DISP_COLOR0 (1)
+
+#define MT8189_DISP_RDMA0_SEL_IN 0xe04
+ #define MT8189_SEL_IN_DISP_RDMA0_FROM_DISP_RSZ0_MOUT (0)
+ #define MT8189_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0_OUT0_MOUT (1)
+#define MT8189_DISP_RDMA_SEL_IN_MASK 0x1
+
+#define MT8189_DISP_RDMA1_RSZ1_SOUT_SEL 0xe08
+ #define MT8189_SOUT_DISP_RDMA1_RSZ1_TO_OVL_PQ_OUT_CROSSBAR4 (0)
+ #define MT8189_SOUT_DISP_RDMA1_RSZ1_TO_DISP_COLOR1 (1)
+
+#define MT8189_DISP_RDMA1_SEL_IN 0xe0c
+ #define MT8189_SEL_IN_DISP_RDMA1_FROM_DISP_RSZ1_MOUT (0)
+ #define MT8189_SEL_IN_DISP_RDMA1_FROM_DISP_OVL1_OUT0_MOUT (1)
+
+#define MT8189_DISP_OVL0_BGCLR_MOUT_EN 0xe24
+ #define MT8189_MOUT_OVL_TO_BLENDOUT BIT(0)
+ #define MT8189_MOUT_OVL_TO_BG BIT(1)
+
+#define MT8189_DISP_OVL1_BGCLR_MOUT_EN 0xe28
+#define MT8189_DISP_OVL_BGCLR_MOUT_MASK 0x3
+
+static const struct mtk_mmsys_routes mmsys_mt8189_routing_table[] = {
+ /* main path */
+ MMSYS_ROUTE(DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8189_DISP_OVL0_BGCLR_MOUT_EN, MT8189_DISP_OVL_BGCLR_MOUT_MASK,
+ MT8189_MOUT_OVL_TO_BLENDOUT),
+ MMSYS_ROUTE(DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8189_DISP_OVL0_OUT0_MOUT_EN, MT8189_DISP_OVL_OUT0_MOUT_MASK,
+ MT8189_MOUT_DISP_OVL0_TO_DISP_RDMA0),
+ MMSYS_ROUTE(DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8189_DISP_RDMA0_SEL_IN, MT8189_DISP_RDMA_SEL_IN_MASK,
+ MT8189_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0_OUT0_MOUT),
+ MMSYS_ROUTE(DDP_COMPONENT_RDMA0, DDP_COMPONENT_COMP0_OUT_CB4,
+ MT8189_DISP_RDMA0_RSZ0_SOUT_SEL, MT8189_OVL_PQ_OUT_CROSSBAR_MOUT_MASK,
+ MT8189_SOUT_DISP_RDMA0_RSZ0_TO_OVL_PQ_OUT_CROSSBAR1),
+ MMSYS_ROUTE(DDP_COMPONENT_RDMA0, DDP_COMPONENT_COMP0_OUT_CB4,
+ MT8189_OVL_PQ_OUT_CROSSBAR1_MOUT_EN, MT8189_OVL_PQ_OUT_CROSSBAR_MOUT_MASK,
+ MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_COMP_OUT_CROSSBAR4),
+ MMSYS_ROUTE(DDP_COMPONENT_COMP0_OUT_CB4, DDP_COMPONENT_DVO0,
+ MT8189_COMP_OUT_CROSSBAR4_MOUT_EN, MT8189_COMP_OUT_CROSSBAR_MOUT_MASK,
+ MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_DVO0),
+ /* ext path */
+ MMSYS_ROUTE(DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+ MT8189_DISP_OVL1_BGCLR_MOUT_EN, MT8189_DISP_OVL_BGCLR_MOUT_MASK,
+ MT8189_MOUT_OVL_TO_BLENDOUT),
+ MMSYS_ROUTE(DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+ MT8189_DISP_OVL1_OUT0_MOUT_EN, MT8189_DISP_OVL_OUT0_MOUT_MASK,
+ MT8189_MOUT_DISP_OVL1_TO_DISP_RDMA1),
+ MMSYS_ROUTE(DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+ MT8189_DISP_RDMA1_SEL_IN, MT8189_DISP_RDMA_SEL_IN_MASK,
+ MT8189_SEL_IN_DISP_RDMA1_FROM_DISP_OVL1_OUT0_MOUT),
+ MMSYS_ROUTE(DDP_COMPONENT_RDMA1, DDP_COMPONENT_COMP0_OUT_CB5,
+ MT8189_DISP_RDMA1_RSZ1_SOUT_SEL, MT8189_OVL_PQ_OUT_CROSSBAR_MOUT_MASK,
+ MT8189_SOUT_DISP_RDMA1_RSZ1_TO_OVL_PQ_OUT_CROSSBAR4),
+ MMSYS_ROUTE(DDP_COMPONENT_RDMA1, DDP_COMPONENT_COMP0_OUT_CB5,
+ MT8189_OVL_PQ_OUT_CROSSBAR4_MOUT_EN, MT8189_OVL_PQ_OUT_CROSSBAR_MOUT_MASK,
+ MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_COMP_OUT_CROSSBAR5),
+ MMSYS_ROUTE(DDP_COMPONENT_COMP0_OUT_CB5, DDP_COMPONENT_DVO1,
+ MT8189_COMP_OUT_CROSSBAR5_MOUT_EN, MT8189_COMP_OUT_CROSSBAR_MOUT_MASK,
+ MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DVO1),
+ MMSYS_ROUTE(DDP_COMPONENT_COMP0_OUT_CB5, DDP_COMPONENT_DSI0,
+ MT8189_COMP_OUT_CROSSBAR5_MOUT_EN, MT8189_COMP_OUT_CROSSBAR_MOUT_MASK,
+ MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DSI0),
+};
+
+static const struct mtk_mmsys_default mmsys_mt8189_disp0_default_table[] = {
+ {MT8189_MMSYS_GCE_EVENT_SEL, MT8189_EVENT_GCE_EN, GENMASK(1, 0)},
+};
+
+#endif /* __SOC_MEDIATEK_MT8189_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 3b490b993549..da5de4061007 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -22,6 +22,7 @@
#include "mt8183-mmsys.h"
#include "mt8186-mmsys.h"
#include "mt8188-mmsys.h"
+#include "mt8189-mmsys.h"
#include "mt8192-mmsys.h"
#include "mt8195-mmsys.h"
#include "mt8196-mmsys.h"
@@ -116,6 +117,16 @@ static const struct mtk_mmsys_driver_data mt8188_vppsys1_driver_data = {
.is_vppsys = true,
};
+static const struct mtk_mmsys_driver_data mt8189_mmsys_driver_data = {
+ .clk_driver = "clk-mt8189-mmsys",
+ .routes = mmsys_mt8189_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8189_routing_table),
+ .def_config = mmsys_mt8189_disp0_default_table,
+ .num_def_config = ARRAY_SIZE(mmsys_mt8189_disp0_default_table),
+ .sw0_rst_offset = MT8189_MMSYS_SW0_RST_B,
+ .num_resets = 32,
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.clk_driver = "clk-mt8192-mm",
.routes = mmsys_mt8192_routing_table,
@@ -668,6 +679,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
{ .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data },
{ .compatible = "mediatek,mt8188-vppsys0", .data = &mt8188_vppsys0_driver_data },
{ .compatible = "mediatek,mt8188-vppsys1", .data = &mt8188_vppsys1_driver_data },
+ { .compatible = "mediatek,mt8189-mmsys", .data = &mt8189_mmsys_driver_data },
{ .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data },
/* "mediatek,mt8195-mmsys" compatible is deprecated */
{ .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data },
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4a0b10567581..7d63b9f0899f 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -49,6 +49,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSI2,
DDP_COMPONENT_DSI3,
DDP_COMPONENT_DVO0,
+ DDP_COMPONENT_DVO1,
DDP_COMPONENT_ETHDR_MIXER,
DDP_COMPONENT_GAMMA,
DDP_COMPONENT_MDP_RDMA0,
@@ -133,6 +134,10 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
+ DDP_COMPONENT_RSZ0,
+ DDP_COMPONENT_RSZ1,
+ DDP_COMPONENT_COMP0_OUT_CB4,
+ DDP_COMPONENT_COMP0_OUT_CB5,
DDP_COMPONENT_ID_MAX,
};
--
2.46.0
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