linux-kernel - Re: [PATCH v2 0/5] rust: pci: add config space read/write support, take 1

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-Id: <DDO24JQ1I3ER.1GOOI7RQISUS@nvidia.com>
Date: Tue, 21 Oct 2025 23:07:27 +0900
From: "Alexandre Courbot" <acourbot@...dia.com>
To: "Zhi Wang" <zhiw@...dia.com>, <rust-for-linux@...r.kernel.org>
Cc: <dakr@...nel.org>, <bhelgaas@...gle.com>, <kwilczynski@...nel.org>,
 <ojeda@...nel.org>, <alex.gaynor@...il.com>, <boqun.feng@...il.com>,
 <gary@...yguo.net>, <bjorn3_gh@...tonmail.com>, <lossin@...nel.org>,
 <a.hindborg@...nel.org>, <aliceryhl@...gle.com>, <tmgross@...ch.edu>,
 <linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
 <cjia@...dia.com>, <smitra@...dia.com>, <ankita@...dia.com>,
 <aniketa@...dia.com>, <kwankhede@...dia.com>, <targupta@...dia.com>,
 <zhiwang@...nel.org>, <acourbot@...dia.com>, <joelagnelf@...dia.com>,
 <jhubbard@...dia.com>, <markus.probst@...teo.de>
Subject: Re: [PATCH v2 0/5] rust: pci: add config space read/write support,
 take 1

On Fri Oct 17, 2025 at 6:02 AM JST, Zhi Wang wrote:
> In the NVIDIA vGPU RFC [1], the PCI configuration space access is
> required in nova-core for preparing gspVFInfo when vGPU support is
> enabled. This series is the following up of the discussion with Danilo
> for how to introduce support of PCI configuration space access in Rust
> PCI abstrations. Bascially, we are thinking of introducing another
> backend for PCI configuration space access similar with Kernel::Io.
>
> This ideas of this series are:
>
> - Factor out a common trait 'Io' for other accessors to share the
>   same compiling/runtime check like before.
>
> - Factor the MMIO read/write macros from the define_read! and
>   define_write! macros. Thus, define_{read, write}! can be used in other
>   backend.
>
> - Add a helper to query configuration space size. This is mostly for
>   runtime check.
>
> - Implement the PCI configuration space access backend in PCI
>   abstractions.
>
> v2:
>
> - Factor out common trait as 'Io' and keep the rest routines in original
>   'Io' as 'Mmio'. (Danilo)
>
> - Rename 'IoRaw' to 'MmioRaw'. Update the bus MMIO implemention to use
>   'MmioRaw'.
>
> - Intorduce pci::Device<Bound>::config_space(). (Danilo)
>
> - Implement both infallible and fallible read/write routines, the device
>   driver devicdes which version should be used.
>
> Moving forward:
>
> - Define and use register! macros.
> - Introduce { cap, ecap } search and read.
>
> RFC v1:
> https://lore.kernel.org/all/20251010080330.183559-1-zhiw@nvidia.com/

One small nit: the title of this series 

    [PATCH v2 0/5] rust: pci: add config space read/write support, take 1

Is a tad confusing. How can this be take 1, if this is a v2? Also there
is no v1, the previous revision was a RFC.

Technically this should have been [PATCH 0/5] or [PATCH v1 0/5]. `b4` is
great to avoid this kind of problems, and a huge time saver generally
speaking. Can't recommend it enough.