linux-kernel - Re: [PATCH 1/6] drm/msm/a6xx: Add support for Adreno 612

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Message-ID: <97aeb6a1-fda2-440f-b14b-2f3dbc2d7e8e@oss.qualcomm.com>
Date: Fri, 24 Oct 2025 04:27:42 +0530
From: Akhil P Oommen <akhilpo@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Rob Clark <robin.clark@....qualcomm.com>, Sean Paul <sean@...rly.run>,
        Konrad Dybcio <konradybcio@...nel.org>,
        Dmitry Baryshkov <lumag@...nel.org>,
        Abhinav Kumar <abhinav.kumar@...ux.dev>,
        Jessica Zhang <jessica.zhang@....qualcomm.com>,
        Marijn Suijten <marijn.suijten@...ainline.org>,
        David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
        Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
        Maxime Ripard <mripard@...nel.org>,
        Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
        freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, Jie Zhang <quic_jiezh@...cinc.com>
Subject: Re: [PATCH 1/6] drm/msm/a6xx: Add support for Adreno 612

On 10/22/2025 8:43 PM, Konrad Dybcio wrote:
> On 10/17/25 7:08 PM, Akhil P Oommen wrote:
>> From: Jie Zhang <quic_jiezh@...cinc.com>
>>
>> Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets.
>> A612 falls under ADRENO_6XX_GEN1 family and is a cut down version
>> of A615 GPU.
>>
>> A612 has a new IP called Reduced Graphics Management Unit or RGMU
>> which is a small state machine which helps to toggle GX GDSC
>> (connected to CX rail) to implement IFPC feature. It doesn't support
>> any other features of a full fledged GMU like clock control, resource
>> voting to rpmh etc. So we need linux clock driver support like other
>> gmu-wrapper implementations to control gpu core clock and gpu GX gdsc.
>> This patch skips RGMU core initialization and act more like a
>> gmu-wrapper case.
>>
>> Co-developed-by: Akhil P Oommen <akhilpo@....qualcomm.com>
>> Signed-off-by: Jie Zhang <quic_jiezh@...cinc.com>
>> Signed-off-by: Akhil P Oommen <akhilpo@....qualcomm.com>
>> ---
> 
> [...]
> 
>> @@ -350,12 +350,18 @@ static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
>>  /* Trigger a OOB (out of band) request to the GMU */
>>  int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
>>  {
>> +	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
>> +	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
>>  	int ret;
>>  	u32 val;
>>  	int request, ack;
>>  
>>  	WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
>>  
>> +	/* Skip OOB calls since RGMU is not enabled */
> 
> "RGMU doesn't handle OOB calls"

Technically RGMU can handle OOB calls. But we are not initializing rgmu.

> 
> [...]
> 
>> +int a6xx_rgmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
>> +{
>> +	struct platform_device *pdev = of_find_device_by_node(node);
>> +	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
>> +	int ret;
>> +
>> +	if (!pdev)
>> +		return -ENODEV;
>> +
>> +	gmu->dev = &pdev->dev;
>> +
>> +	ret = of_dma_configure(gmu->dev, node, true);
>> +	if (ret)
>> +		return ret;
>> +
>> +	pm_runtime_enable(gmu->dev);
>> +
>> +	/* Mark legacy for manual SPTPRAC control */
>> +	gmu->legacy = true;
>> +
>> +	/* RGMU requires clocks */
>> +	ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
>> +	if (ret < 1)
>> +		return ret;
> 
> Simply add this clock detail to a6xx_gmu_wrapper_init and use _optional

Hmm. It looks like devm_clk_bulk_get_all() returns 0 if there are no
clocks. Will squash.

> 
> [...]
> 
>>  	/* Enable fault detection */
>>  	if (adreno_is_a730(adreno_gpu) ||
>> -	    adreno_is_a740_family(adreno_gpu))
>> +	    adreno_is_a740_family(adreno_gpu) || adreno_is_a612(adreno_gpu))
> 
> Sorting this would be neat

Ack

> 
> [...]
> 
>> +static int a6xx_rgmu_pm_resume(struct msm_gpu *gpu)
>> +{
>> +	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>> +	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>> +	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
>> +	unsigned long freq = gpu->fast_rate;
>> +	struct dev_pm_opp *opp;
>> +	int ret;
>> +
>> +	gpu->needs_hw_init = true;
>> +
>> +	trace_msm_gpu_resume(0);
>> +
>> +	opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq);
>> +	if (IS_ERR(opp))
>> +		return PTR_ERR(opp);
>> +
>> +	dev_pm_opp_put(opp);
>> +
>> +	/* Set the core clock and bus bw, having VDD scaling in mind */
>> +	dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
>> +
>> +	pm_runtime_resume_and_get(gmu->dev);
>> +	pm_runtime_resume_and_get(gmu->gxpd);
>> +
>> +	ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
>> +	if (ret)
>> +		goto err_rpm_put;
>> +
>> +	ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
>> +	if (ret)
>> +		goto err_bulk_clk;
> 
> Add this as-is to a6xx_pm_resume(), nr_clocks==0 is valid, similarly
> for _suspend

The other difference is a6xx_llc_activate/deactivate(). Looks to me that
we can unconditionally add that too to a6xx_pm_resume().

-Akhil

> 
> Konrad