linux-kernel - Re: [PATCH v4 6/7] dt-bindings: clock: rockchip: Add RK3506 clock and reset unit

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Message-ID: <20251024-wonderful-banana-bumblebee-273c8f@kuoka>
Date: Fri, 24 Oct 2025 09:14:05 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Elaine Zhang <zhangqing@...k-chips.com>
Cc: mturquette@...libre.com, sboyd@...nel.org, sugar.zhang@...k-chips.com, 
	heiko@...ech.de, robh@...nel.org, krzysztof.kozlowski+dt@...aro.org, 
	conor+dt@...nel.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
	linux-clk@...r.kernel.org, linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	huangtao@...k-chips.com, finley.xiao@...k-chips.com
Subject: Re: [PATCH v4 6/7] dt-bindings: clock: rockchip: Add RK3506 clock
 and reset unit

On Tue, Oct 21, 2025 at 02:52:31PM +0800, Elaine Zhang wrote:
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml
> new file mode 100644
> index 000000000000..43e192d9b2af
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,rk3506-cru.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip RK3506 Clock and Reset Unit (CRU)
> +
> +maintainers:
> +  - Finley Xiao <finley.xiao@...k-chips.com>
> +  - Heiko Stuebner <heiko@...ech.de>
> +
> +description: |

Do not need '|' unless you need to preserve formatting.

> +  The RK3506 CRU generates the clock and also implements reset for SoC
> +  peripherals.
> +

...

> diff --git a/include/dt-bindings/clock/rockchip,rk3506-cru.h b/include/dt-bindings/clock/rockchip,rk3506-cru.h
> new file mode 100644
> index 000000000000..f629b6fa75c3
> --- /dev/null
> +++ b/include/dt-bindings/clock/rockchip,rk3506-cru.h
> @@ -0,0 +1,285 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.
> + * Author: Finley Xiao <finley.xiao@...k-chips.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H
> +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H
> +
> +/* cru plls */
> +#define PLL_GPLL			1

Other binding starts from 0, so be consistent.

> +#define PLL_V0PLL			2
> +#define PLL_V1PLL			3
> +
> +/* cru-clocks indices */

You should not have holes in indices. These are abstract numbers, not
hardware values.


> +#define ARMCLK				15

...


> +#ifndef _DT_BINDINGS_REST_ROCKCHIP_RK3506_H
> +#define _DT_BINDINGS_REST_ROCKCHIP_RK3506_H
> +
> +/* CRU-->SOFTRST_CON00 */
> +#define SRST_NCOREPORESET0_AC		0

Here ^^^ starts with 0, not 1.

Best regards,
Krzysztof