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Message-ID: <e9306983-e2df-4235-a58b-e0b451380b52@oss.qualcomm.com>
Date: Tue, 28 Oct 2025 23:12:23 +0530
From: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
To: Bjorn Andersson <andersson@...nel.org>,
cros-qcom-dts-watchers@...omium.org,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Lorenzo Pieralisi
<lpieralisi@...nel.org>,
Manivannan Sadhasivam <mani@...nel.org>,
Krzysztof WilczyĆski <kwilczynski@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>, Jingoo Han <jingoohan1@...il.com>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
quic_vbadigan@...cinc.com, quic_mrana@...cinc.com,
quic_vpernami@...cinc.com, mmareddy@...cinc.com,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: (subset) [PATCH v8 0/5] PCI: dwc: Add ECAM support with iATU
configuration
On 10/28/2025 4:07 AM, Bjorn Andersson wrote:
> On Thu, 28 Aug 2025 13:04:21 +0530, Krishna Chaitanya Chundru wrote:
>> The current implementation requires iATU for every configuration
>> space access which increases latency & cpu utilization.
>>
>> Designware databook 5.20a, section 3.10.10.3 says about CFG Shift Feature,
>> which shifts/maps the BDF (bits [31:16] of the third header DWORD, which
>> would be matched against the Base and Limit addresses) of the incoming
>> CfgRd0/CfgWr0 down to bits[27:12]of the translated address.
>>
>> [...]
> Applied, thanks!
>
> [1/5] arm64: dts: qcom: sc7280: Increase config size to 256MB for ECAM feature
> commit: 03e928442d469f7d8dafc549638730647202d9ce
Hi Bjorn,
Can you revert this change, this is regression due to this series due to
that we have change the logic,
we need to update the dtsi accordingly, I will send a separate for all
controllers to enable this ECAM feature.
- Krishna Chaitanya.
> Best regards,
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