linux-kernel - [PATCH 1/8] arm64: dts: imx8qm-mek: add state_100mhz and state

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Message-Id: <20251028-b4_qm_dts-v1-1-51ba94389c1f@nxp.com>
Date: Tue, 28 Oct 2025 16:30:42 -0400
From: Frank Li <Frank.Li@....com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>, 
 Sascha Hauer <s.hauer@...gutronix.de>, 
 Pengutronix Kernel Team <kernel@...gutronix.de>, 
 Fabio Estevam <festevam@...il.com>
Cc: devicetree@...r.kernel.org, imx@...ts.linux.dev, 
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, 
 Frank Li <Frank.Li@....com>
Subject: [PATCH 1/8] arm64: dts: imx8qm-mek: add state_100mhz and
 state_200mhz for usdhc

default, state_100mhz and state_200mhz use the same settings. But current
driver use these to indicate if sd3.0 support.

Signed-off-by: Frank Li <Frank.Li@....com>
---
 arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 202d5c67ac40b844ee38e8fb0f9caf2e186cfa9f..6f1c78fcf384a7691f7f8ea1b50ab21cd6e72ba1 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -800,8 +800,10 @@ &pwm_lvds1 {
 };
 
 &usdhc1 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	pinctrl-2 = <&pinctrl_usdhc1>;
 	bus-width = <8>;
 	no-sd;
 	no-sdio;
@@ -810,8 +812,10 @@ &usdhc1 {
 };
 
 &usdhc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 	bus-width = <4>;
 	vmmc-supply = <&reg_usdhc2_vmmc>;
 	cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
@@ -1228,4 +1232,12 @@ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
 			IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
 		>;
 	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21			0x00000021
+			IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22			0x00000021
+			IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07			0x00000021
+		>;
+	};
 };

-- 
2.34.1