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Message-Id: <20251028-b4_qm_dts-v1-2-51ba94389c1f@nxp.com>
Date: Tue, 28 Oct 2025 16:30:43 -0400
From: Frank Li <Frank.Li@....com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>
Cc: devicetree@...r.kernel.org, imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Frank Li <Frank.Li@....com>
Subject: [PATCH 2/8] arm64: dts: imx8qm-mek: assign double SD bus frequency
for usdhc1
Assign double SD bus frequency to support SDR104 mode, where the operating
clock runs at 208 MHz.
Signed-off-by: Frank Li <Frank.Li@....com>
---
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 6f1c78fcf384a7691f7f8ea1b50ab21cd6e72ba1..44b8e9c75c59aa31cf9dd04c3d03be047ef82ff9 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -800,6 +800,8 @@ &pwm_lvds1 {
};
&usdhc1 {
+ assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
--
2.34.1
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