linux-kernel - RE: [PATCH 00/19] Add RZ/G3E RSCI support

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Message-ID:
 <TYCPR01MB113320C083F52CBF7B8CD8CA586FDA@TYCPR01MB11332.jpnprd01.prod.outlook.com>
Date: Tue, 28 Oct 2025 09:12:24 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
CC: Jiri Slaby <jirislaby@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>, Prabhakar Mahadev Lad
	<prabhakar.mahadev-lad.rj@...renesas.com>, wsa+renesas
	<wsa+renesas@...g-engineering.com>, Claudiu Beznea
	<claudiu.beznea.uj@...renesas.com>, Nam Cao <namcao@...utronix.de>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-serial@...r.kernel.org" <linux-serial@...r.kernel.org>, biju.das.au
	<biju.das.au@...il.com>, "linux-renesas-soc@...r.kernel.org"
	<linux-renesas-soc@...r.kernel.org>
Subject: RE: [PATCH 00/19] Add RZ/G3E RSCI support

Hi Greg,

Thanks for the feedback.

> -----Original Message-----
> From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
> Sent: 28 October 2025 08:42
> Subject: Re: [PATCH 00/19] Add RZ/G3E RSCI support
> 
> On Mon, Oct 27, 2025 at 03:45:47PM +0000, Biju Das wrote:
> > Add RZ/G3E RSCI support for FIFO and non-FIFO mode. RSCI IP found on
> > RZ/G3E SoC is similar to one on RZ/T2H, but has 32-stage fifo. RZ/G3E
> > has
> > 5 module clocks compared to 2 on RZ/T2H, and it has multiple resets.
> > Add support for hardware flow control.
> >
> > Biju Das (19):
> >   clk: renesas: r9a09g047: Add RSCI clocks/resets
> 
> Why is a clk patch part of a serial series?  How are we supposed to merge this thing?

OK, will split the series into clock, driver fix, dt-binding fix , 
dt-binding + driver patches for the next and dts patches.

Cheers,
Biju