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Message-Id: <20251029-knp-ipcc-v2-2-8ba303ab82de@oss.qualcomm.com>
Date: Wed, 29 Oct 2025 01:15:10 -0700
From: Jingyi Wang <jingyi.wang@....qualcomm.com>
To: Manivannan Sadhasivam <mani@...nel.org>,
Jassi Brar <jassisinghbrar@...il.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: aiqun.yu@....qualcomm.com, tingwei.zhang@....qualcomm.com,
trilok.soni@....qualcomm.com, yijie.yang@....qualcomm.com,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, Jingyi Wang <jingyi.wang@....qualcomm.com>,
Sibi Sankar <sibi.sankar@....qualcomm.com>
Subject: [PATCH v2 2/2] dt-bindings: mailbox: qcom: Add IPCC support for
Glymur Platform
From: Sibi Sankar <sibi.sankar@....qualcomm.com>
Add binding and physical client ids for the Glymur platform. Physical
client IDs instead of virtual client IDs are used for qcom new platforms
in the Inter Process Communication Controller (IPCC) driver as virtual to
physical mapping logic is removed in HW.
Signed-off-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@....qualcomm.com>
---
.../devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
include/dt-bindings/mailbox/qcom,glymur-ipcc.h | 68 ++++++++++++++++++++++
2 files changed, 69 insertions(+)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
index ee3fe093e3ca..7c4d6170491d 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
@@ -24,6 +24,7 @@ properties:
compatible:
items:
- enum:
+ - qcom,glymur-ipcc
- qcom,kaanapali-ipcc
- qcom,milos-ipcc
- qcom,qcs8300-ipcc
diff --git a/include/dt-bindings/mailbox/qcom,glymur-ipcc.h b/include/dt-bindings/mailbox/qcom,glymur-ipcc.h
new file mode 100644
index 000000000000..3ab8189974a5
--- /dev/null
+++ b/include/dt-bindings/mailbox/qcom,glymur-ipcc.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DT_BINDINGS_MAILBOX_IPCC_GLYMUR_H
+#define __DT_BINDINGS_MAILBOX_IPCC_GLYMUR_H
+
+/* Glymur physical client IDs */
+#define IPCC_MPROC_AOP 0
+#define IPCC_MPROC_TZ 1
+#define IPCC_MPROC_MPSS 2
+#define IPCC_MPROC_LPASS 3
+#define IPCC_MPROC_SLPI 4
+#define IPCC_MPROC_SDC 5
+#define IPCC_MPROC_CDSP 6
+#define IPCC_MPROC_NPU 7
+#define IPCC_MPROC_APSS 8
+#define IPCC_MPROC_GPU 9
+#define IPCC_MPROC_ICP 11
+#define IPCC_MPROC_VPU 12
+#define IPCC_MPROC_PCIE0 13
+#define IPCC_MPROC_PCIE1 14
+#define IPCC_MPROC_PCIE2 15
+#define IPCC_MPROC_SPSS 16
+#define IPCC_MPROC_PCIE3 19
+#define IPCC_MPROC_PCIE4 20
+#define IPCC_MPROC_PCIE5 21
+#define IPCC_MPROC_PCIE6 22
+#define IPCC_MPROC_TME 23
+#define IPCC_MPROC_WPSS 24
+#define IPCC_MPROC_PCIE7 44
+#define IPCC_MPROC_SOCCP 46
+
+#define IPCC_COMPUTE_L0_LPASS 0
+#define IPCC_COMPUTE_L0_CDSP 1
+#define IPCC_COMPUTE_L0_APSS 2
+#define IPCC_COMPUTE_L0_GPU 3
+#define IPCC_COMPUTE_L0_CVP 6
+#define IPCC_COMPUTE_L0_ICP 7
+#define IPCC_COMPUTE_L0_VPU 8
+#define IPCC_COMPUTE_L0_DPU 9
+#define IPCC_COMPUTE_L0_SOCCP 11
+
+#define IPCC_COMPUTE_L1_LPASS 0
+#define IPCC_COMPUTE_L1_CDSP 1
+#define IPCC_COMPUTE_L1_APSS 2
+#define IPCC_COMPUTE_L1_GPU 3
+#define IPCC_COMPUTE_L1_CVP 6
+#define IPCC_COMPUTE_L1_ICP 7
+#define IPCC_COMPUTE_L1_VPU 8
+#define IPCC_COMPUTE_L1_DPU 9
+#define IPCC_COMPUTE_L1_SOCCP 11
+
+#define IPCC_PERIPH_LPASS 0
+#define IPCC_PERIPH_APSS 1
+#define IPCC_PERIPH_PCIE0 2
+#define IPCC_PERIPH_PCIE1 3
+#define IPCC_PERIPH_PCIE2 6
+#define IPCC_PERIPH_PCIE3 7
+#define IPCC_PERIPH_PCIE4 8
+#define IPCC_PERIPH_PCIE5 9
+#define IPCC_PERIPH_PCIE6 10
+#define IPCC_PERIPH_PCIE7 11
+#define IPCC_PERIPH_SOCCP 13
+#define IPCC_PERIPH_WPSS 16
+
+#endif
--
2.25.1
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