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Message-Id: <20251029-knp-ipcc-v2-1-8ba303ab82de@oss.qualcomm.com>
Date: Wed, 29 Oct 2025 01:15:09 -0700
From: Jingyi Wang <jingyi.wang@....qualcomm.com>
To: Manivannan Sadhasivam <mani@...nel.org>,
Jassi Brar <jassisinghbrar@...il.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: aiqun.yu@....qualcomm.com, tingwei.zhang@....qualcomm.com,
trilok.soni@....qualcomm.com, yijie.yang@....qualcomm.com,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, Jingyi Wang <jingyi.wang@....qualcomm.com>
Subject: [PATCH v2 1/2] dt-bindings: mailbox: qcom: Add IPCC support for
Kaanapali Platform
Add the physical client ids and binding for Kaanapali platform. Physical
client IDs instead of virtual client IDs are used for qcom new platforms
in the Inter Process Communication Controller (IPCC) driver as virtual to
physical mapping logic is removed in HW.
Signed-off-by: Jingyi Wang <jingyi.wang@....qualcomm.com>
---
.../devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
include/dt-bindings/mailbox/qcom,kaanapali-ipcc.h | 58 ++++++++++++++++++++++
2 files changed, 59 insertions(+)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
index e5c423130db6..ee3fe093e3ca 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
@@ -24,6 +24,7 @@ properties:
compatible:
items:
- enum:
+ - qcom,kaanapali-ipcc
- qcom,milos-ipcc
- qcom,qcs8300-ipcc
- qcom,qdu1000-ipcc
diff --git a/include/dt-bindings/mailbox/qcom,kaanapali-ipcc.h b/include/dt-bindings/mailbox/qcom,kaanapali-ipcc.h
new file mode 100644
index 000000000000..b6208ad155ad
--- /dev/null
+++ b/include/dt-bindings/mailbox/qcom,kaanapali-ipcc.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DT_BINDINGS_MAILBOX_IPCC_KAANAPALI_H
+#define __DT_BINDINGS_MAILBOX_IPCC_KAANAPALI_H
+
+/* Physical client IDs */
+#define IPCC_MPROC_AOP 0
+#define IPCC_MPROC_TZ 1
+#define IPCC_MPROC_MPSS 2
+#define IPCC_MPROC_LPASS 3
+#define IPCC_MPROC_SDC 4
+#define IPCC_MPROC_CDSP 5
+#define IPCC_MPROC_APSS 6
+#define IPCC_MPROC_SOCCP 13
+#define IPCC_MPROC_DCP 14
+#define IPCC_MPROC_SPSS 15
+#define IPCC_MPROC_TME 16
+#define IPCC_MPROC_WPSS 17
+
+#define IPCC_COMPUTE_L0_CDSP 2
+#define IPCC_COMPUTE_L0_APSS 3
+#define IPCC_COMPUTE_L0_GPU 4
+#define IPCC_COMPUTE_L0_CVP 8
+#define IPCC_COMPUTE_L0_CAM 9
+#define IPCC_COMPUTE_L0_CAM1 10
+#define IPCC_COMPUTE_L0_DCP 11
+#define IPCC_COMPUTE_L0_VPU 12
+#define IPCC_COMPUTE_L0_SOCCP 16
+
+#define IPCC_COMPUTE_L1_CDSP 2
+#define IPCC_COMPUTE_L1_APSS 3
+#define IPCC_COMPUTE_L1_GPU 4
+#define IPCC_COMPUTE_L1_CVP 8
+#define IPCC_COMPUTE_L1_CAM 9
+#define IPCC_COMPUTE_L1_CAM1 10
+#define IPCC_COMPUTE_L1_DCP 11
+#define IPCC_COMPUTE_L1_VPU 12
+#define IPCC_COMPUTE_L1_SOCCP 16
+
+#define IPCC_PERIPH_CDSP 2
+#define IPCC_PERIPH_APSS 3
+#define IPCC_PERIPH_PCIE0 4
+#define IPCC_PERIPH_PCIE1 5
+
+#define IPCC_FENCE_CDSP 2
+#define IPCC_FENCE_APSS 3
+#define IPCC_FENCE_GPU 4
+#define IPCC_FENCE_CVP 8
+#define IPCC_FENCE_CAM 8
+#define IPCC_FENCE_CAM1 10
+#define IPCC_FENCE_DCP 11
+#define IPCC_FENCE_VPU 20
+#define IPCC_FENCE_SOCCP 24
+
+#endif
--
2.25.1
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