linux-kernel - Re: [PATCH RFC/WIP 0/4] arm64: dts: qcom: sm8750: Enable display

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Message-ID: <CAO9ioeWdJpKfpu3jGyv42Mf5+02ehxyEu_Lj+Boz0NyDjPZ-CQ@mail.gmail.com>
Date: Thu, 30 Oct 2025 13:16:49 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Mahadevan P <mahadevan.p@....qualcomm.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        jesszhan0024@...il.com, quic_rajeevny@...cinc.com,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Abhinav Kumar <abhinavk@...cinc.com>, Abel Vesa <abel.vesa@...aro.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH RFC/WIP 0/4] arm64: dts: qcom: sm8750: Enable display

Hi Mahadevan,

On Wed, 29 Oct 2025 at 08:20, Mahadevan P <mahadevan.p@....qualcomm.com> wrote:
>
> Hi Krzysztof,
>
> On 4/26/2025 1:24 AM, Krzysztof Kozlowski wrote:
>
> On 25/04/2025 21:34, Dmitry Baryshkov wrote:
>
> On Thu, Apr 24, 2025 at 03:04:24PM +0200, Krzysztof Kozlowski wrote:

Could you please fix your email client to _never_ send HTML emails.
You've destroyed all the quoting (quotation?) levels. Your email was
caught by the automatic mailing list filters, etc.

> We at Qualcomm are currently working on bringing up the DSI display on MTP. For this, I’ve picked the following patches on top of v6.18-rc2:
>
> All the DT changes mentioned in this series
> [PATCH v2] drm/msm/dpu: Fix adjusted mode clock check for 3d merge
> https://lore.kernel.org/all/1154f275-f934-46ae-950a-209d31463525@kernel.org/
> [PATCH v2 0/2] drm/panel: Add Novatek NT37801 panel driver
> https://lore.kernel.org/all/20250508-sm8750-display-panel-v2-0-3ca072e3d1fa@linaro.org/
>
> However, when testing with modetest, the panel appears blank. I wanted to check if there are any additional patches already posted that I might have missed and should be included.

Any errors or warnings in dmesg?

>
> Also, I’m curious to understand more about the DSI PHY PLL VCO rate issue that Jessica had narrowed down—could you please share some details?
>
> Lastly, I’d appreciate it if you could share the plan for merging these changes upstream. We’re aiming to enable display support on this target as part of our program.

Please see Documentation/process/, I think it describes the process of
merging patches pretty well.

-- 
With best wishes
Dmitry