linux-kernel - RE: [PATCH v2 12/13] serial: sh-sci: Add support for RZ/G3E RSCI SCIF

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID:
 <TY3PR01MB11346585ED62E65396655EA2A86F8A@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Fri, 31 Oct 2025 07:16:52 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Jiri Slaby <jirislaby@...nel.org>, biju.das.au <biju.das.au@...il.com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>
CC: wsa+renesas <wsa+renesas@...g-engineering.com>, Prabhakar Mahadev Lad
	<prabhakar.mahadev-lad.rj@...renesas.com>, Geert Uytterhoeven
	<geert+renesas@...der.be>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "linux-serial@...r.kernel.org"
	<linux-serial@...r.kernel.org>, "linux-renesas-soc@...r.kernel.org"
	<linux-renesas-soc@...r.kernel.org>
Subject: RE: [PATCH v2 12/13] serial: sh-sci: Add support for RZ/G3E RSCI SCIF

Hi Jiri Slaby,

Thanks for the feedback.

> -----Original Message-----
> From: Jiri Slaby <jirislaby@...nel.org>
> Sent: 31 October 2025 04:51
> Subject: Re: [PATCH v2 12/13] serial: sh-sci: Add support for RZ/G3E RSCI SCIF
> 
> Hi,
> 
> On 30. 10. 25, 18:58, Biju wrote:
> > From: Biju Das <biju.das.jz@...renesas.com>
> >
> > Add support for RZ/G3E RSCI SCIF(a.k.a FIFO mode). RSCI IP found on
> > the RZ/G3E SoC is similar to RZ/T2H, but it has a 32-stage FIFO. it
> > has 6
> > clocks(5 module clocks + 1 external clock) instead of 3 clocks(2
> > module clocks + 1 external clock) on T2H and has multiple resets. Add
> > support for the hardware flow control.
> >
> > Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> > ---
> ...
> > --- a/drivers/tty/serial/rsci.c
> > +++ b/drivers/tty/serial/rsci.c
> > @@ -11,6 +11,8 @@
> ...
> > +static void rsci_finish_console_write(struct uart_port *port, u32
> > +ctrl) {
> > +	rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE);
> > +	cpu_relax();
> 
> What's the intent of cpu_relax in here? It does not make much sense to me. If you need delay, use
> delay.

Just to add synchronization delay after setting TE=0. OK I will use delay here.

> 
> > +	rsci_serial_out(port, CCR0, ctrl);
> > +}
> > +
> ...
> > diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> > index fac83dace27c..85b89c1ebf15 100644
> > --- a/drivers/tty/serial/sh-sci.c
> > +++ b/drivers/tty/serial/sh-sci.c
> > @@ -3397,7 +3397,7 @@ static void sci_remove(struct platform_device *dev)
> >   	if (s->port.fifosize > 1)
> >   		device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
> >   	if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF ||
> > -	    type == SCI_PORT_RSCI)
> > +	    type == SCI_PORT_RSCI || type == RSCI_PORT_SCIF)
> >   		device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
> ...
> > @@ -3759,7 +3763,8 @@ static int sci_probe(struct platform_device *dev)
> >   			return ret;
> >   	}
> >   	if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB ||
> > -	    sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI) {
> > +	    sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI ||
> > +	    sp->type == RSCI_PORT_SCIF) {
> 
> This test is duplicated -- you seem you need a helper for this.

OK, will add helper for this.

Cheers,
Biju