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Message-Id: <20251031-optimize_pll_driver-v3-2-92f3b2f36a83@amlogic.com>
Date: Fri, 31 Oct 2025 16:10:09 +0800
From: Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@...nel.org>
To: Neil Armstrong <neil.armstrong@...aro.org>,
Jerome Brunet <jbrunet@...libre.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Kevin Hilman <khilman@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc: linux-amlogic@...ts.infradead.org, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Chuan Liu <chuan.liu@...ogic.com>
Subject: [PATCH v3 2/4] clk: amlogic: Improve the issue of PLL lock
failures
From: Chuan Liu <chuan.liu@...ogic.com>
Due to factors such as temperature and process variations, the
internal circuits of the PLL may require a longer time to reach a
steady state, which can result in occasional lock failures on some
SoCs under low-temperature conditions.
After enabling the PLL and releasing its reset, a 20 us delay is
added at each step to provide enough time for the internal PLL
circuit to stabilize, thus reducing the probability of PLL lock
failure.
Signed-off-by: Chuan Liu <chuan.liu@...ogic.com>
---
drivers/clk/meson/clk-pll.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 629f6af18ea1..70c8c7078046 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -369,10 +369,17 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
/* Enable the pll */
meson_parm_write(clk->map, &pll->en, 1);
+ /* Wait for Bandgap and LDO to power up and stabilize */
+ udelay(20);
+
/* Take the pll out reset */
- if (MESON_PARM_APPLICABLE(&pll->rst))
+ if (MESON_PARM_APPLICABLE(&pll->rst)) {
meson_parm_write(clk->map, &pll->rst, 0);
+ /* Wait for PLL loop stabilization */
+ udelay(20);
+ }
+
/*
* Compared with the previous SoCs, self-adaption current module
* is newly added for A1, keep the new power-on sequence to enable the
--
2.42.0
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