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Message-ID: <20251101162829.3076855-1-neal.frager@amd.com>
Date: Sat, 1 Nov 2025 16:28:29 +0000
From: Neal Frager <neal.frager@....com>
To: <gregkh@...uxfoundation.org>, <linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>, <git@....com>
CC: <michal.simek@....com>, <jguittet@...ekio.com>,
<jay.buddhabhatti@....com>, <arun.balaji.kannan@....com>,
<senthilnathan.thangaraj@....com>, <thomas.hommel@...rson.com>,
<micheal.saleab@....com>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, Neal Frager <neal.frager@....com>
Subject: [PATCH v1 1/1] arm64: dts: xilinx: fix zynqmp opp-table-cpu
Since the following commit, the zynqmp clk driver uses the common
divider_round_rate() when determining the appropriate clock divider for a
requested clock frequency:
https://github.com/torvalds/linux/commit/1fe15be1fb613534ecbac5f8c3f8744f757d237d
This means that the typical parent clock rate will be 1200000000 based on the
zynqmp pll configuration. If the current zynqmp.dtsi opp-hz values are used,
this will mean the divider calculations are always slightly above the correct
integer divider value meaning they will get rounded up to a divider value
which is one to high. The result of this issue is that the cpu clock speed
will always be one opp lower than the requested clock rate.
For example, the following will occur when requesting 1.2 GHz with the current
zynqmp.dtsi:
root@...qmp:/sys/kernel/tracing# cat /sys/devices/system/cpu/cpufreq/policy0/scaling_available_frequencies
299999 399999 599999 1199999
root@...qmp:/ # echo 1200000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed
root@...qmp:/ # cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq
600000
To fix this issue, this patch updates the zynqmp opp-table-cpu, so the clock
rates are calculated correctly.
root@...qmp:/sys/kernel/tracing# cat /sys/devices/system/cpu/cpufreq/policy0/scaling_available_frequencies
300000 400000 600000 1200000
root@...qmp:/ # echo 1200000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed
root@...qmp:/ # cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq
1200000
Signed-off-by: Neal Frager <neal.frager@....com>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 38 +++++++++++++-------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 938b014ca923..484901dcbdba 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -103,25 +103,25 @@ CPU_SLEEP_0: cpu-sleep-0 {
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
- opp00 {
- opp-hz = /bits/ 64 <1199999988>;
- opp-microvolt = <1000000>;
- clock-latency-ns = <500000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <599999994>;
- opp-microvolt = <1000000>;
- clock-latency-ns = <500000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <399999996>;
- opp-microvolt = <1000000>;
- clock-latency-ns = <500000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <299999997>;
- opp-microvolt = <1000000>;
- clock-latency-ns = <500000>;
+ opp-1200000000 {
+ opp-hz = <0x00 0x47868c00>;
+ clock-latency-ns = <0x7a120>;
+ opp-microvolt = <0xf4240>;
+ };
+ opp-600000000 {
+ opp-hz = <0x00 0x23c34600>;
+ clock-latency-ns = <0x7a120>;
+ opp-microvolt = <0xf4240>;
+ };
+ opp-400000000 {
+ opp-hz = <0x00 0x17d78400>;
+ clock-latency-ns = <0x7a120>;
+ opp-microvolt = <0xf4240>;
+ };
+ opp-300000000 {
+ opp-hz = <0x00 0x11e1a300>;
+ clock-latency-ns = <0x7a120>;
+ opp-microvolt = <0xf4240>;
};
};
--
2.25.1
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