linux-kernel - [PATCH v3 1/2] dt-bindings: phy: qcom-edp: Add eDP ref clk for sa8775p

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20251104114327.27842-2-riteshk@qti.qualcomm.com>
Date: Tue,  4 Nov 2025 17:13:26 +0530
From: Ritesh Kumar <riteshk@....qualcomm.com>
To: robin.clark@....qualcomm.com, lumag@...nel.org, abhinav.kumar@...ux.dev,
        jessica.zhang@....qualcomm.com, sean@...rly.run,
        marijn.suijten@...ainline.org, maarten.lankhorst@...ux.intel.com,
        mripard@...nel.org, tzimmermann@...e.de, airlied@...il.com,
        simona@...ll.ch, robh@...nel.org, krzk+dt@...nel.org,
        conor+dt@...nel.org, quic_mahap@...cinc.com, andersson@...nel.org,
        konradybcio@...nel.org, mani@...nel.org,
        James.Bottomley@...senPartnership.com, martin.petersen@...cle.com,
        vkoul@...nel.org, kishon@...nel.org,
        cros-qcom-dts-watchers@...omium.org
Cc: Ritesh Kumar <quic_riteshk@...cinc.com>, linux-phy@...ts.infradead.org,
        linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
        freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-scsi@...r.kernel.org,
        quic_vproddut@...cinc.com
Subject: [PATCH v3 1/2] dt-bindings: phy: qcom-edp: Add eDP ref clk for sa8775p

From: Ritesh Kumar <quic_riteshk@...cinc.com>

When the initial contribution of eDP PHY for sa8775p was done,
eDP reference clock voting was missed. It worked fine at that
time because the clock was already enabled by the UFS PHY driver.

After commit 77d2fa54a945 ("scsi: ufs: qcom : Refactor
phy_power_on/off calls"), eDP reference clock started getting
turned off, leading to the following PHY power-on failure:

phy phy-aec2a00.phy.10: phy poweron failed --> -110

To fix this, explicit voting for the eDP reference clock is
required. This patch adds the eDP reference clock for sa8775p
eDP PHY and updates the corresponding example node.

Signed-off-by: Ritesh Kumar <quic_riteshk@...cinc.com>
---
 .../devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml  | 6 ++++--
 Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml     | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
index e2730a2f25cf..6c827cf9692b 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -200,9 +200,11 @@ examples:
                   <0x0aec2000 0x1c8>;
 
             clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
-                     <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+                     <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+                     <&gcc GCC_EDP_REF_CLKREF_EN>;
             clock-names = "aux",
-                          "cfg_ahb";
+                          "cfg_ahb",
+                          "ref";
 
             #clock-cells = <1>;
             #phy-cells = <0>;
diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
index bfc4d75f50ff..ba757b08b9b1 100644
--- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
@@ -72,6 +72,7 @@ allOf:
       properties:
         compatible:
           enum:
+            - qcom,sa8775p-edp-phy
             - qcom,x1e80100-dp-phy
     then:
       properties:
-- 
2.17.1