linux-kernel - Re: [PATCH v5 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region

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Message-ID: <20251105-flying-asp-of-poetry-cd9d2e@kuoka>
Date: Wed, 5 Nov 2025 09:25:55 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Khairul Anuar Romli <khairul.anuar.romli@...era.com>
Cc: Dinh Nguyen <dinguyen@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Mahesh Rao <mahesh.rao@...era.com>, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, 
	Adrian Ng Ho Yin <adrianhoyin.ng@...era.com>, Niravkumar L Rabara <niravkumarlaxmidas.rabara@...era.com>
Subject: Re: [PATCH v5 2/2] arm64: dts: intel: Add Agilex5 SVC node with
 memory region

On Wed, Nov 05, 2025 at 10:28:02AM +0800, Khairul Anuar Romli wrote:
> Introduce the Stratix10 SoC Service Layer (SVC) node for Agilex5 SoCs. This
> node includes the compatible string "intel,agilex5-svc" and references a
> reserved memory region used for communication with the Secure Device
> Manager (SDM).
> 
> Agilex5 introduces changes in how reserved memory is mapped and accessed
> compared to previous SoC generations, particularly with the addition of
> IOMMU support. Unlike earlier platforms, Agilex5 enables the use of the
> Translation Buffer Unit (TBU) in non-secure mode, allowing Linux to access
> it through the IOMMU framework. This commit updates the device tree
> structure to support Agilex5-specific handling of the SVC interface,
> including the necessary bindings for IOMMU integration.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@...era.com>
> ---
> Changes in v5:
> 	- No change.
> Changes in v4:
> 	- Exclude peers reviewers in the sign off.
> Changes in v3:
> 	- include iommu property in svc node.
> 	- Rephrase git commit message to describe iommu presence
> 	  in Agilex5
> Changes in v2:
> 	- Rephrase commit message to exclude mentioning iommu
> ---
>  arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index a13ccee3c4c3..15284092897e 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -841,5 +841,14 @@ queue7 {
>  				};
>  			};
>  		};
> +
> +		firmware {

Did you just add node to the end of the file? No. Place it somewhere
after cpus, see DTS coding style.

Another problem that you have here warnings, which tools would tell you.
Please use tools instead of humans, see maintainer soc profiles (both)
for more explanation.

Best regards,
Krzysztof