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Message-ID: <725a5700-0504-4bbf-bcd3-fa036fa74a23@ti.com>
Date: Thu, 6 Nov 2025 19:32:32 +0530
From: Swamil Jain <s-jain1@...com>
To: <jyri.sarha@....fi>, <tomi.valkeinen@...asonboard.com>,
<maarten.lankhorst@...ux.intel.com>, <mripard@...nel.org>,
<tzimmermann@...e.de>, <airlied@...il.com>, <simona@...ll.ch>, <nm@...com>,
<vigneshr@...com>, <kristo@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>, <lee@...nel.org>,
<louis.chauvet@...tlin.com>, <aradhya.bhatia@...ux.dev>
CC: <devarsht@...com>, <praneeth@...com>, <h-shenoy@...com>,
<dri-devel@...ts.freedesktop.org>, <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 0/5] drm/tidss: Fixes data edge sampling on AM62X and
AM62A
Hi All,
On 11/6/25 19:16, Swamil Jain wrote:
> Currently the driver only configure the data edge sampling partially.
> AM62X, AM62A and AM62P require it to be configured in two distinct
> registers: one in tidss and one in the Control MMR registers.
>
> Introduce a new dt property to link the proper syscon node from the main
> device registers into the tidss driver.
>
> The series targets to fix the issue for AM62X and AM62A, later will add
> the changes required for AM62P after DSS support gets upstreamed.
>
> Fixes: ad2ac9dc9426 ("drm/tidss: Add support for AM625 DSS")
> Fixes: 5cc5ea7b6d7b ("drm/tidss: Add support for AM62A7 DSS")
> ---
> Cc: stable@...r.kernel.org
>
> Signed-off-by: Louis Chauvet <louis.chauvet@...tlin.com>
> Signed-off-by: Swamil Jain <s-jain1@...com>
> ---
Please ignore this series, will resend v2.
Regards,
Swamil
>
> Louis Chauvet (4):
> dt-bindings: display: ti,am65x-dss: Add clk property for data edge
> synchronization
> dt-bindings: mfd: syscon: Add ti,am625-dss-clk-ctrl
> arm64: dts: ti: k3-am62-main: Add tidss clk-ctrl property
> drm/tidss: Fix sampling edge configuration
>
> Swamil Jain (1):
> arm64: dts: ti: k3-am62a-main: Add tidss clk-ctrl property
>
> .../bindings/display/ti/ti,am65x-dss.yaml | 6 ++++++
> Documentation/devicetree/bindings/mfd/syscon.yaml | 3 ++-
> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 6 ++++++
> arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 7 +++++++
> drivers/gpu/drm/tidss/tidss_dispc.c | 14 ++++++++++++++
> 5 files changed, 35 insertions(+), 1 deletion(-)
>
>
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> From: Swamil Jain <s-jain1@...com>
> To: <jyri.sarha@....fi>, <tomi.valkeinen@...asonboard.com>,
> <maarten.lankhorst@...ux.intel.com>, <mripard@...nel.org>,
> <tzimmermann@...e.de>, <airlied@...il.com>, <simona@...ll.ch>, <nm@...com>,
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> <krzk+dt@...nel.org>, <conor+dt@...nel.org>, <lee@...nel.org>,
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> CC: <devarsht@...com>, <praneeth@...com>, <h-shenoy@...com>,
> <dri-devel@...ts.freedesktop.org>, <linux-arm-kernel@...ts.infradead.org>,
> <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
> Subject: [PATCH v2 1/5] dt-bindings: display: ti,am65x-dss: Add clk property for data edge synchronization
> Date: Thu, 6 Nov 2025 19:16:48 +0530
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> From: Louis Chauvet <louis.chauvet@...tlin.com>
>
> The dt-bindings for the display, specifically ti,am65x-dss, need to
> include a clock property for data edge synchronization. The current
> implementation does not correctly apply the data edge sampling property.
>
> To address this, synchronization of writes to two different registers is
> required: one in the TIDSS IP (which is already described in the tidss
> node) and one is in the Memory Mapped Control Register Modules.
>
> As the Memory Mapped Control Register Modules is located in a different
> IP, we need to use a phandle to write values in its registers.
>
> Fixes: ad2ac9dc9426 ("drm/tidss: Add support for AM625 DSS")
> Fixes: 5cc5ea7b6d7b ("drm/tidss: Add support for AM62A7 DSS")
> Cc: stable@...r.kernel.org
> Signed-off-by: Louis Chauvet <louis.chauvet@...tlin.com>
> Signed-off-by: Swamil Jain <s-jain1@...com>
> ---
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> index 361e9cae6896..b9a373b56917 100644
> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> @@ -133,6 +133,12 @@ properties:
> and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
> interface to work.
>
> + ti,clk-ctrl:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to syscon device node mapping CFG0_CLK_CTRL registers.
> + This property is needed for proper data sampling edge.
> +
> max-memory-bandwidth:
> $ref: /schemas/types.yaml#/definitions/uint32
> description:
>
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> Subject: [PATCH v2 2/5] dt-bindings: mfd: syscon: Add ti,am625-dss-clk-ctrl
> Date: Thu, 6 Nov 2025 19:16:49 +0530
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> From: Louis Chauvet <louis.chauvet@...tlin.com>
>
> The dt-bindings for the multi-function device (mfd) syscon need to include
> ti,am625-dss-clk-ctrl. On AM62X, AM62A and AM62P devicess, the display
> controller (tidss) has external registers to control certain clock
> properties. These registers are located in the device configuration
> registers, so they need to be declared using syscon. They will later be
> used with a phandle in the tidss node.
>
> Fixes: ad2ac9dc9426 ("drm/tidss: Add support for AM625 DSS")
> Fixes: 5cc5ea7b6d7b ("drm/tidss: Add support for AM62A7 DSS")
> Cc: stable@...r.kernel.org
> Signed-off-by: Louis Chauvet <louis.chauvet@...tlin.com>
> Signed-off-by: Swamil Jain <s-jain1@...com>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> index 657c38175fba..2dace701b9a6 100644
> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> @@ -123,6 +123,7 @@ select:
> - ti,am62-opp-efuse-table
> - ti,am62-usb-phy-ctrl
> - ti,am625-dss-oldi-io-ctrl
> + - ti,am625-dss-clk-ctrl
> - ti,am62p-cpsw-mac-efuse
> - ti,am654-dss-oldi-io-ctrl
> - ti,j784s4-acspcie-proxy-ctrl
> @@ -232,6 +233,7 @@ properties:
> - ti,am62-opp-efuse-table
> - ti,am62-usb-phy-ctrl
> - ti,am625-dss-oldi-io-ctrl
> + - ti,am625-dss-clk-ctrl
> - ti,am62p-cpsw-mac-efuse
> - ti,am654-dss-oldi-io-ctrl
> - ti,j784s4-acspcie-proxy-ctrl
> @@ -260,4 +262,3 @@ examples:
> compatible = "allwinner,sun8i-h3-system-controller", "syscon";
> reg = <0x01c00000 0x1000>;
> };
> -...
>
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> Subject: [PATCH v2 3/5] arm64: dts: ti: k3-am62-main: Add tidss clk-ctrl property
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> From: Louis Chauvet <louis.chauvet@...tlin.com>
>
> For am62 processors, we need to use the newly created clk-ctrl property to
> properly handle data edge sampling configuration. Add them in the main
> device tree.
>
> Fixes: ad2ac9dc9426 ("drm/tidss: Add support for AM625 DSS")
> Cc: stable@...r.kernel.org
> Signed-off-by: Louis Chauvet <louis.chauvet@...tlin.com>
> Signed-off-by: Swamil Jain <s-jain1@...com>
> ---
> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> index a290a674767b..2b6c033ae393 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> @@ -77,6 +77,11 @@ audio_refclk1: clock-controller@...4 {
> #clock-cells = <0>;
> };
>
> + dss_clk_ctrl: dss-clk-ctrl@...0 {
> + compatible = "ti,am625-dss-clk-ctrl", "syscon";
> + reg = <0x8300 0x4>;
> + };
> +
> dss_oldi_io_ctrl: oldi-io-controller@...0 {
> compatible = "ti,am625-dss-oldi-io-ctrl", "syscon";
> reg = <0x8600 0x200>;
> @@ -801,6 +806,7 @@ dss: dss@...00000 {
> <&k3_clks 186 2>;
> clock-names = "fck", "vp1", "vp2";
> interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> + ti,clk-ctrl = <&dss_clk_ctrl>;
> status = "disabled";
>
> oldi-transmitters {
>
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> To: <jyri.sarha@....fi>, <tomi.valkeinen@...asonboard.com>,
> <maarten.lankhorst@...ux.intel.com>, <mripard@...nel.org>,
> <tzimmermann@...e.de>, <airlied@...il.com>, <simona@...ll.ch>, <nm@...com>,
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> CC: <devarsht@...com>, <praneeth@...com>, <h-shenoy@...com>,
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> <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
> Subject: [PATCH v2 1/5] dt-bindings: display: ti,
> am65x-dss: Add clk property for data edge synchronization
> Date: Thu, 6 Nov 2025 19:16:48 +0530
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> From: Louis Chauvet <louis.chauvet@...tlin.com>
>
> The dt-bindings for the display, specifically ti,am65x-dss, need to
> include a clock property for data edge synchronization. The current
> implementation does not correctly apply the data edge sampling property.
>
> To address this, synchronization of writes to two different registers is
> required: one in the TIDSS IP (which is already described in the tidss
> node) and one is in the Memory Mapped Control Register Modules.
>
> As the Memory Mapped Control Register Modules is located in a different
> IP, we need to use a phandle to write values in its registers.
>
> Fixes: ad2ac9dc9426 ("drm/tidss: Add support for AM625 DSS")
> Fixes: 5cc5ea7b6d7b ("drm/tidss: Add support for AM62A7 DSS")
> Cc: stable@...r.kernel.org
> Signed-off-by: Louis Chauvet <louis.chauvet@...tlin.com>
> Signed-off-by: Swamil Jain <s-jain1@...com>
> ---
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> index 361e9cae6896..b9a373b56917 100644
> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> @@ -133,6 +133,12 @@ properties:
> and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
> interface to work.
>
> + ti,clk-ctrl:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to syscon device node mapping CFG0_CLK_CTRL registers.
> + This property is needed for proper data sampling edge.
> +
> max-memory-bandwidth:
> $ref: /schemas/types.yaml#/definitions/uint32
> description:
>
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> From: Swamil Jain <s-jain1@...com>
> To: <jyri.sarha@....fi>, <tomi.valkeinen@...asonboard.com>,
> <maarten.lankhorst@...ux.intel.com>, <mripard@...nel.org>,
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> Subject: [PATCH v2 4/5] arm64: dts: ti: k3-am62a-main: Add tidss clk-ctrl property
> Date: Thu, 6 Nov 2025 19:16:51 +0530
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> For AM62A, we need to use the newly created clk-ctrl property to
> properly handle data edge sampling configuration. Add them in main
> device tree.
>
> Fixes: 5cc5ea7b6d7b ("drm/tidss: Add support for AM62A7 DSS")
> Cc: stable@...r.kernel.org
> Signed-off-by: Swamil Jain <s-jain1@...com>
> ---
> arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
> index 9e5b75a4e88e..15a9ee35dbce 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
> @@ -77,6 +77,12 @@ audio_refclk1: clock-controller@...4 {
> assigned-clock-parents = <&k3_clks 157 18>;
> #clock-cells = <0>;
> };
> +
> + dss_clk_ctrl: dss-clk-ctrl@...0 {
> + compatible = "ti,am625-dss-clk-ctrl", "syscon";
> + reg = <0x8300 0x4>;
> + };
> +
> };
>
> dmss: bus@...00000 {
> @@ -1136,6 +1142,7 @@ dss: dss@...00000 {
> <&k3_clks 186 2>;
> clock-names = "fck", "vp1", "vp2";
> interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> + ti,clk-ctrl = <&dss_clk_ctrl>;
> status = "disabled";
>
> dss_ports: ports {
>
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> From: Swamil Jain <s-jain1@...com>
> To: <jyri.sarha@....fi>, <tomi.valkeinen@...asonboard.com>,
> <maarten.lankhorst@...ux.intel.com>, <mripard@...nel.org>,
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> Subject: [PATCH v2 5/5] drm/tidss: Fix sampling edge configuration
> Date: Thu, 6 Nov 2025 19:16:52 +0530
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> From: Louis Chauvet <louis.chauvet@...tlin.com>
>
> As stated in the AM62x Technical Reference Manual (SPRUIV7B)[1], the data
> sampling edge needs to be configured in two distinct registers: one in the
> TIDSS IP and another in the memory-mapped control register modules. Since
> the latter is not within the same address range, a phandle to a syscon
> device is used to access the regmap.
>
> Configure the CTRL_MMR register, as mentioned in the Technical Reference
> Manual to fix sampling edge.
>
> [1]: https://www.ti.com/lit/ug/spruiv7b/spruiv7b.pdf
>
> Fixes: ad2ac9dc9426 ("drm/tidss: Add support for AM625 DSS")
> Fixes: 5cc5ea7b6d7b ("drm/tidss: Add support for AM62A7 DSS")
> Cc: stable@...r.kernel.org
> Signed-off-by: Louis Chauvet <louis.chauvet@...tlin.com>
> Signed-off-by: Swamil Jain <s-jain1@...com>
> ---
> drivers/gpu/drm/tidss/tidss_dispc.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
> index d8e1a1bcd660..d09eecb72dc0 100644
> --- a/drivers/gpu/drm/tidss/tidss_dispc.c
> +++ b/drivers/gpu/drm/tidss/tidss_dispc.c
> @@ -500,6 +500,7 @@ struct dispc_device {
> const struct dispc_features *feat;
>
> struct clk *fclk;
> + struct regmap *clk_ctrl;
>
> bool is_enabled;
>
> @@ -1234,6 +1235,11 @@ void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
> mode->crtc_hdisplay - 1) |
> FIELD_PREP(DISPC_VP_SIZE_SCREEN_VDISPLAY_MASK,
> mode->crtc_vdisplay - 1));
> +
> + if (dispc->clk_ctrl) {
> + regmap_update_bits(dispc->clk_ctrl, 0, 0x100, ipc ? 0x100 : 0x000);
> + regmap_update_bits(dispc->clk_ctrl, 0, 0x200, rf ? 0x200 : 0x000);
> + }
> }
>
> void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport)
> @@ -3003,6 +3009,14 @@ int dispc_init(struct tidss_device *tidss)
>
> dispc_init_errata(dispc);
>
> + dispc->clk_ctrl = syscon_regmap_lookup_by_phandle_optional(tidss->dev->of_node,
> + "ti,clk-ctrl");
> + if (IS_ERR(dispc->clk_ctrl)) {
> + r = dev_err_probe(dispc->dev, PTR_ERR(dispc->clk_ctrl),
> + "DISPC: syscon_regmap_lookup_by_phandle failed.\n");
> + return r;
> + }
> +
> dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats),
> sizeof(*dispc->fourccs), GFP_KERNEL);
> if (!dispc->fourccs)
>
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