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Message-ID: <20251106101917.GB15456@unreal>
Date: Thu, 6 Nov 2025 12:19:17 +0200
From: Leon Romanovsky <leon@...nel.org>
To: Gerd Bayer <gbayer@...ux.ibm.com>
Cc: Saeed Mahameed <saeedm@...dia.com>, Tariq Toukan <tariqt@...dia.com>,
Mark Bloch <mbloch@...dia.com>, Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Jason Gunthorpe <jgg@...pe.ca>, Bjorn Helgaas <bhelgaas@...gle.com>,
Jay Cornwall <Jay.Cornwall@....com>,
Felix Kuehling <Felix.Kuehling@....com>,
Niklas Schnelle <schnelle@...ux.ibm.com>,
Alexander Schmidt <alexs@...ux.ibm.com>, netdev@...r.kernel.org,
linux-rdma@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH RFC 2/2] ib/mlx5: Request PCIe AtomicOps enabled for all
3 sizes
On Wed, Nov 05, 2025 at 06:55:14PM +0100, Gerd Bayer wrote:
> Pass fully populated capability bit-mask requesting support for all 3
> sizes of AtomicOps at once when attempting to enable AtomicOps for PCI
> function.
>
> When called individually, pci_enable_atomic_ops_to_root() may enable the
> device to send requests as soon as one size is supported. According to
> PCIe Spec 7.0 Section 6.15.3.1 support of 32-bit and 64-bit AtomicOps
> completer capabilities are tied together for root-ports. Only the
> 128-bit/CAS completer capabilities is an optional feature, but still we
> might end up end up enabling AtomicOps despite 128-bit/CAS is not
> supported at the root-port.
>
> Signed-off-by: Gerd Bayer <gbayer@...ux.ibm.com>
> ---
> drivers/infiniband/hw/mlx5/data_direct.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/infiniband/hw/mlx5/data_direct.c b/drivers/infiniband/hw/mlx5/data_direct.c
> index b81ac5709b56f6ac0d9f60572ce7144258fa2794..112185be53f1ccc6a797e129f24432bdc86008ae 100644
> --- a/drivers/infiniband/hw/mlx5/data_direct.c
> +++ b/drivers/infiniband/hw/mlx5/data_direct.c
> @@ -179,9 +179,9 @@ static int mlx5_data_direct_probe(struct pci_dev *pdev, const struct pci_device_
> if (err)
> goto err_disable;
>
> - if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
> - pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
> - pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
> + if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
> + PCI_EXP_DEVCAP2_ATOMIC_COMP64 |
> + PCI_EXP_DEVCAP2_ATOMIC_COMP128))
I would expect some new define which combines all together, with some
comment why it exists:
#define PCI_ATOMIC_COMP_v7 PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64 | PCI_EXP_DEVCAP2_ATOMIC_COMP128
Anyway the change looks right to me.
Thanks,
Acked-by: Leon Romanovsky <leon@...nel.org>
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