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Message-ID: <aRHdiYYcn2uZkLor@wunner.de>
Date: Mon, 10 Nov 2025 13:41:45 +0100
From: Lukas Wunner <lukas@...ner.de>
To: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
Cc: andersson@...nel.org, robh@...nel.org, manivannan.sadhasivam@...aro.org,
	krzk@...nel.org, helgaas@...nel.org, linux-arm-msm@...r.kernel.org,
	devicetree@...r.kernel.org, lpieralisi@...nel.org, kw@...ux.com,
	conor+dt@...nel.org, linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org, devicetree-spec@...r.kernel.org,
	quic_vbadigan@...cinc.com
Subject: Re: [PATCH v2] schemas: pci: Document PCIe T_POWER_ON

On Mon, Nov 10, 2025 at 04:59:47PM +0530, Krishna Chaitanya Chundru wrote:
> From PCIe r6, sec 5.5.4 & Table 5-11 in sec 5.5.5 T_POWER_ON is the

Please use the latest spec version as reference, i.e. PCIe r7.0.

> minimum amount of time(in us) that each component must wait in L1.2.Exit
> after sampling CLKREQ# asserted before actively driving the interface to
> ensure no device is ever actively driving into an unpowered component and
> these values are based on the components and AC coupling capacitors used
> in the connection linking the two components.
> 
> This property should be used to indicate the T_POWER_ON for each Root Port.

What's the difference between this property and the Port T_POWER_ON_Scale
and T_POWER_ON_Value in the L1 PM Substates Capabilities Register?

Why do you need this in the device tree even though it's available
in the register?

Thanks,

Lukas

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